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To: K. M. Strickler who wrote (17228)	2/7/1998 2:56:00 PM
From: Daniel Schuh	Read Replies (4) \| Respond to of 24154

Ken, either you're confused or I am. Yes, disks have one head per recording surface, but the alignment at modern densities is sufficiently tricky that only one head on the assembly can maintain the correct position relative to its corresponding disk surface. I.e. the electronics have to sense the track and do a fine alignment adjustment, that's what settle time is. Aligning one track doesn't align the whole cylinder; thermal expansion and mechanical factors make it hard for the arm assembly to do that. At least that's what I was told by architecture guys. Copper vs. aluminum is on-chip interconnect technology. Bus mastering dma means what it says; the i/o controller becomes the master of the memory bus, instead of the CPU. This is actually true for any DMA PCI device, but with IDE/UDMA implemented in the chip set it gets a little confused. It "cycle steals" in the sense that the memory bus is a shared resource, and has to be arbitrated, but the cpu doesn't need the bus every cycle anyway, caches and all that . This isn't like the old PC/isa dma channels, which I never understood. PIO mode is a tremendous CPU hog because you have to hang the cpu doing (relatively) slow word at a time transfers, not because of the number of instructions need. AGP/MMX channel sounds like a separate data path out of the CPU to the video device. I'd guess it's preferable to keep the disk path independent of the CPU, but I don't know the processor microarchitecture, I couldn't say for sure. Or maybe they're just overloading MMX and it's independent of MMX in the processor, I don't know. Anyway, the memory interfaces and bus speeds will be improved as time goes on too. Cheers, Dan.