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To: Paul Engel who wrote (47529)	2/10/1998 12:52:00 PM
From: Tony Viola	Read Replies (2) \| Respond to of 186894

Paul, RE: "The Cacheless Covington chip will be slower - memory accesses will have to occur from main memory - which will run at 66 or 100 MHz instead of the 133 MHz (assuming a 266 MHz CPU speed)." Don't forget that there will still be an L1 cache on board with the PII Covington. What size, I don't know. So, there is still a buffer memory (old mainframe term). Speaking of mainframes, even they didn't have L2 cache until recently, about the last 3 years. Tony