Ibexx and Intel Investors - If Intel's New CPU Dissipated 90 Watts...
The entire world would be up in arms decrying Intel's lousy technology, their poor designs, and their inferior architecture.
Journalists would be "burning the Internet Oil", adding joke upon joke to Intel's new "Space Heaters" and OPEC-eating power power consumption.
However, if DEC puts out a 90 Watter, what loud protests doth we hear?
Aye...not a one, laddy!
Read all about DEC's Alpha Light Bulb!
Paul
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zdnet.com
Performance, not power issues,
drive chip architects
By Ron Wilson and Peter Clarke
SAN FRANCISCO -- Will power consumption limit
microprocessor performance?
"Yes!" was the answer from a panel at last week's
International Solid-State Circuits Conference. But
despite the power limits, the panel agreed that
maximizing performance remains the primary goal of
microprocessor design teams.
The panel's conclusion was encapsulated by a member
of the audience who observed: "If you've ever watched
a kid playing Quake for hours on end, you'll know it's
true-performance is a drug. We've got to go on
delivering two times performance at each generation or
we won't be able to sell systems."
The panel displayed a high-end microprocessor bias,
however. Most members were drawn from workstation-
and server-oriented design teams, and as such were
not primarily concerned with issues of battery life. But
the question posed to panel members provided a
jumping off point for exploring how power consumption
issues would manifest themselves-and what tricks
design teams can deploy to ward off the power limit.
The panelists concluded that power consumption need
not yet be a limit, then admitted that it had already
happened. Randy Allmon, consulting engineer at Digital
Equipment's Hudson design center, said Digital
Equipment's recently announced 21264 Alpha CPU
has run into power issues.
"The chip dissipates about 72 watts under normal
conditions," Allmon said. "But under the worst-case
conditions for which we have to design, it can
theoretically peak at over 90 W-at the top end of the
range where air cooling is effective. We had to turn
down the supply voltage from the 2.5 V the process was
designed for, to 2.2 V to keep the dissipation down to
90 W maximum. So, in effect, we are already
power-limited."
But a number of speakers, including Allmon, suggested
techniques that could be used to reduce power
consumption, delaying the day when the problem
comes up again. Proposals ranged from more
aggressive heat removal-with water or heat pipes, for
example-to better overall budgeting of power in the
design, as well as lower operating voltages and use of
radically different circuit techniques.
The panel agreed that architects were adding many
transistors for minimal improvements in chip
performance. But in the race for highest SPEC figures,
that was what they were paid to do. Motorola designer
David Beardon warned, "You have to manage power in
the microarchitecture, or not at all."
The closest the panel got to controversy was when
panelist Kerry Bernstein, senior engineer at IBM
Microelectronics said: "Circuit designers have done
their homework," and then, with tongue in cheek, called
on process technologists to "fix the technology."
He was followed by the lone process engineer on the
panel, Intel's Mark Bohr, who pointed out that designers
can't keep looking to process engineers for help.
Already, he said, switching energy per transition has
been going down by a factor of two every generation.
Power keeps increasing because architects keep
using more transistors, and using them at higher
switching factors.
At a more detailed level, Bernstein stated that many of
the non-cycle-limiting nets in a typical design were
much faster than they need to be, and hence waste
power.
In addition, Bernstein pointed out, monotonic circuits
avoid the duplication and excess power dissipation of
static CMOS, and offer an alternative in some areas.
Shashank Goel, founder of Simplex Solutions Inc.,
agreed that designers need to choose circuit
techniques carefully, considering dynamic circuits
instead of static, and even looking at such techniques
as domino logic, adiabatic circuits and asynchronous
design.
In addition, Sun Microsystems team leader Ray Heald
warned that simply reducing supply voltage wasn't
going to be a solution much longer. "Reducing voltage
is creating a noise margin problem," he said. "And I
think we are getting close to the edge on signal
integrity. We need to start looking at things like massive
decoupling capacitors on the die, use of signal
repeaters, and moving to pseudo-differential or fully
differential signaling to combat this problem."
But the panel was in general agreement that as long as
the pressure to perform was paramount, architects
would push the power consumption to the edge of what
the package could carry away, leaving it to
microarchitects, circuit designers and process
designers to bring the power back down. They would
not begin to architect power savings into the CPUs until
that was the only way to increase performance further.
The crux came when process technologist Bohr asked
the other panelists how much additional gate delay they
would be prepared to accept for a 10 percent reduction
in power consumption. "None," was the answer that
came back. |
