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Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: David S. who wrote (47597)	2/10/1998 7:37:00 PM
From: Paul Engel	Read Replies (1) \| Respond to of 186894

David - Re: " then would they sell it for about $50 wholesale and would it cost about $100 - $125 retail?" My guess is that Intel will sell the 440 BX for $35 to $50. Historically, chip set prices have been very modest. Intel will make and sell these not to make outlandish profits on the chip sets, but to make the cost of the motherboards "reasonable". Remember - selling the Pentium II/Deschutes that plugs into a 440BX motherboard is Intel's primary objective. As for retail - there is not much of a retail market for chip sets these days. The 440 BX will probably be packaged in a plastic BGA package with >300 solder bumps (not really pins). This is a surface mount package so it does not really lend itself to the home hobbyist for buying and making his own circuit boards. As for screwdriver shops, I would expect the typical "high price" to be the rule of the road for completed motherboards initially, with the costs declining over time. In the recent past, ASUS seems to have been the most aggressive using the 440LX - with motherboards selling for around $249 (single Pentium II) to $379 for Dual Pentium II motherboards (440LX with AGP connectors). I would guess that the 440BX motherboards (Slot 1) will start off at around $279 - $299 a piece - single Deschutes slot. Don't forget - 100 MHz SDRAM DIMMS will be required. Paul

To: David S. who wrote (47597)	2/10/1998 7:40:00 PM
From: Paul Engel	Respond to of 186894

David and Intel Investors - Details about Intel's Slot 2 L2 Cache SRAM chip Finally a review of Intel's ISSCC presentation discussing the 450 MHz (that's FAST) SRAM chip that will be used in the Deschutes/Slot 2 package. These will cost-a-lot and sell for a bundle! Paul {========================} techweb.cmp.com Intel bets on custom cache SRAM for Slot 2 platform By Anthony Cataldo SAN FRANCISCO -- Intel Corp. has staked the success of its next-generation platform for the Pentium II processor on a semi-synchronous device that will run at the same speed as the processor. Unlike the pipelined-burst synchronous L2 cache SRAMs used for current Pentium II processors, Intel will manufacture the new SRAMs in-house for the life of the so-called Slot 2 high-end platform, company officials said Friday. Intel presented a paper that described its custom SRAM (CSRAM) at the International Solid-State Circuits Conference last Friday. The CSRAM is a 512-kbyte, four-way set associative L2 cache that will transfer data to the Pentium II at 3.6-Gbytes per second via a dedicated 72-bit source-synchronous bus. The 2.5-V device will be built on Intel's 0.35-micron four-level metal process, and will dissipate 4.5 W at 450 MHz, a frequency that Intel hopes to hit by the end of the year for both its Pentium II processor and cache memory. Unlike the pipelined-burst synchronous SRAMs the company now uses for its Pentium II processors, the new L2 cache chips is based on a semi-synchronous design in which most of the access path is asynchronous rather than pipelined. This improves speed by eliminating the setup and hold times at each clock cycle. It also requires fewer latches and flip-flops to reduce the clock loading and local clock buffer crossover currents for a 75 percent reduction in the data array, the company said. "With out-of-order execution processors, cache is essential and will continue to be important," said Mike Fister, vice president of product development for Intel (Santa Clara, Calif.). A cache data request can be initiated every four clock cycles, with tag operations interleaved between data requests. If the tag array signals a hit, then data from a single way is selected and multiplexed to the processor in the fifth through eight clock cycles for a five-cycle latency. Data array access and tag array access occur in parallel. Array signals are self-timed and the first 72-bit chunk is re-synchronized to the clock, while subsequent chunks are sequenced out based on order of the requests. "We deliberately made it so that pieces are accessed one at a time," Fister said. "At times there will be multiple accesses so there will be some overlap, but not everything has to be accessed at once." One of the biggest challenges to the design was controlling the electrical characteristics. Intel said it has minimized the skew between the clock and data on-chip by matching the delay paths. Also, the output buffer impedance is programmed by external resistors and uses a closed-loop control. To keep control over the manufacturing, Intel plans to start producing the devices using its own 0.35-micron process technology and will not contract with outside memory manufacturers as it now does with pipelined-burst SRAMs for Pentium IIs. "It's hard to envision getting a whole industry manufacturing these devices" he said. "This is an SRAM for high-end servers and workstations, so it's a bit more of a niche." Intel plans to start manufacturing its first Pentium II processors with the CSRAM by mid-year, which will coincide with a move to 100-MHz system bus that will take advantage of 100-MHz SDRAMs. The cache sizes will start with 512 kbytes for the initial iteration, and will move to 1 Mbyte and 2 Mbytes by the end of the year.