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To: DiViT who wrote (29536)	2/16/1998 4:35:00 PM
From: Alex Dominguez	Respond to of 50808

courtesy of recent EETimes report: Sony, NEC detail MPEG-2 solutions at ISSCC By Yoshiko Hara SAN FRANCISCO -- Sony Corp. and NEC Corp. each made presentations on single-chip MPEG-2 encoder solutions at the International Solid-State Circuits Conference (ISSCC) last week. NEC has developed a dedicated MPEG-2 codec with a small die size and low power consumption, while Sony came up with a DSP-based solution that can be programmed to handle MPEG-2 encoding for various applications. Sony engineers developed a single-chip DSP, which features 2.2-giga operations/second (Gops) performance. The DSP's speed enables software-based, programmable real-time encoding at the main-program-at-main-level (MP@ML) standard, with the important exception of motion estimation. "We went with a software solution, rather than with a dedicated chip, so that the device can be used with various applications," said Seiichiro Iwase, chief research scientist at Sony Media Processing Laboratories. "Image-processing ASICs take a lot of gates and time to design, while doing encoding with the CPU puts too much of a load on the central processor. So we decided to take an intermediate approach -- an application-specific DSP." Motion-estimation (ME) functions were separated from the DSP "because there are various ME algorithms which users can select," Iwata said. Sony's DSP was fabricated on a 0.4-micron, three-metal-layer CMOS logic process, and it operates at 81 MHz on a 3.3V power supply. The die measures 14.43 x 14.75 mm and holds 3.79 million transistors, about two-thirds of which are dedicated to memory. The part is packaged in a 256-lead pin-grid array. The DSP is based on a vector processing unit (VPU) and a separate variable-length coding/decoding unit; both of the units are proprietary designs. The VPU has six processor elements, or one for each macro block. A macro block is the minimum processing unit in MPEG compression; it consists of four Y and two C blocks. The six processor elements are controlled in single-instruction, multiple-data (SIMD) mode. The SIMD architecture can be upgraded by increasing the number of processor elements, Iwata said. The processing units are designed to execute the required encoding algorithms within every macro block in the real-time processing period. For MPEG-2 MP@ML encoding of NTSC video, that's 24.7 microseconds. As a result, the amount of buffer memory needed for the macro-block-level pipeline was reduced. Sony can build a complete MPEG-2 video encoding system by adding a motion-estimation subsystem, a 16-Mbit synchronous DRAM, a 4-Mbit DRAM, and the DSP. Although the DSP is the codec for MP@ML, Iwata said future generations of the architecture could be used with U.S.-developed HDTV standards. NEC developed a 1.5-W single-chip MPEG-2 MP@ML video encoder with a 12.45- x 12.45-mm die size. The 3.1 million transistor device was built in 0.35-micron, triple-level-metal CMOS. Masakazu Yamashina, a manager at NEC's system Ultra-LSI Research Laboratory, said power consumption was kept to a minimum by using an adaptive search-area motion-estimation method, and by a demand clocking scheme. Motion estimation, especially the search for motion vectors, places a heavy execution burden on an MPEG codec. NEC made the search area smaller by reducing the size of the search window when a portion of the image is not moving. By searching windows whose size has been optimized, processing can be cut in half and power consumption reduced by about 25 percent. By focusing on a smaller portion of the image, the picture quality is improved by about 0.5 dB. The encoder compares the image data with previous data to find the motion vector. The data is processed in parallel with eight 16-bit processing elements. Power consumption is kept to a manageable level by distributing the load among the various elements, and by using an algorithm to map the data efficiently. The motion-estimation unit operates on a 2.5-V power supply. Clock distribution usually accounts for about 30 percent of total power consumption. A demand-clock controller was included with each of the ME and DCT units on the chip. When an operation ends, a sleep request is generated within the unit itself. This scheme can reduce power for clock distribution by about 20 percent. Yamashina said an encoder system can be built with the single-chip codec LSI, two 16-Mbyte synchronous DRAMs, a microprocessor, and an audio encoder LSI. "Technologically speaking, a sample will be ready by the end of this year, and NEC intends to put this device on the market in 1998," he said.

To: DiViT who wrote (29536)	2/16/1998 4:44:00 PM
From: John Rieman	Respond to of 50808

A little more about Intel's Developers Forum.................................. news.com Intel: 3D chips the next wave By Michael Kanellos Staff Writer, CNET NEWS.COM February 16, 1998, 11:35 a.m. PT 3D graphics will be one of the main themes of the Intel Developer Forum which kicks off tomorrow in San Jose, California. Following up on last week's release of the Intel740, the company's first 3D chip, Intel will use the three-day conference to present its case that richer and more complex 3D graphics will increasingly become a more integral part of desktop and notebook functionality. In addition, company engineers will show how these developments will impact other computing technology, such as memory. The event will feature keynote speeches from CEO Andy Grove, who will speak tomorrow at 9 a.m., Dr. Albert Yu, senior vice president and general manager of the microprocessor products group, and Pat Gelsinger, vice president and general manger of the business platform group. One of the key conference tracks will occur on Wednesday, when Intel employees and others will present talks on the next generation of the Accelerated Graphics Port (AGP), called AGP 4X. Under AGP, graphics data is carried on a separate, dedicated bus rather than on the system bus. (A bus is a data pathway.) In the end, the system design leads to sharper graphics and faster processing of images. AGP 4X will succeed AGP 2X, which is being used on current high-end desktop systems. Jim Nucci, AGP marketing manager, business platform group, will open the session with a discussion on the performance improvements that will come with AGP 4X as well as give a preliminary overview of the AGP 2.0 specification, the technical outline for AGP 4X. David Smith, chief technology officer at Virtus, will follow with a discussion on the future for AGP and 3D graphics in the business market. The company specializes in 3D presentation software for the corporate arena. Smith will outline Virtus's own product plans for AGP-enabled products. Jon Peddie, president of Jon Peddie Associates, a Tiburon, California-based market research firm, will then round out the track with an overview of the 3D market. Sessions outlining the future for mobile graphics will be presented on Tuesday by Ted Kirkiles, a manager in the mobile hardware products group. Along with the graphics emphasis, various presentations will be made on the state of server technology. Ahmet Houssein, from server architecture lab at Intel, will discuss design guidelines for high-volume servers based around Intel chips. Other topics include an update on the I2O Initative, an architecture which dedicates a separate processor for data input-output, and an outline for common specifications for server design. The semiannual conference will take place from February 17 to 19 at the San Jose Convention Center. Intel is an investor in CNET: The Computer Network.