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To: Petz who wrote (4453)	2/17/1998 4:42:00 PM
From: Paul Engel	Respond to of 6843

Petz - Re: "what is the technical advantage of Slot 1 if semiconductor" First, to add additional L2 cache directly to the CPU, the L2 cache controller and cache TAG SRAMS have to be added to the CPU, essentially creating a major change in architecture. Don't forget - the existing K6 doesn't know if you glue on L2 SRAM to the K6. All the controllers, bus interfaces, etc. have to be grafted on as well - a fairly major redesign. The risk of not getting it done right the first time is greater, and can cause serious delays in product introduction. Slot 1 already has that (L2 cache controller/tag rams) architected in so the Deschutes CAN graft the L2 SRAM and tag rams on to Deschutes chips - the L2 controller is already there. It just needs to be "connected up" to the new L2 SRAM section. Moreover, Slot 1 has more to it than a backside L2 cache bus. It has a transaction based I/O with a high speed GTL+ interface. I/O operations can be generated, one after another, without waiting for previous I/O operations to be completed. The I/O ops can then be completed in an out of order sequence, keeping the I/O bus from "hanging" when one operation is slow or delayed. Slot 1/Deschutes/Pentium also have SMP support so that up to 4 (or 8) Deschutes can exist on one board with no hardware interface. The coherency of the L2 caches (on a Card or grafted on to the CPU) is automatically maintained as the Deschutes "snoops" the I/O buses, flagging data that may go to one of the other L2 caches, indicating a non-coherent situation (local cache would have "dirty" data). The appropriate Deschutes can then generate its own main memory "read" operation to refresh its own L2 cache with the most current (clean) data. These are a few of the relevant differences. Paul