Paul, Article...Intel Lays Out Plans For New Processors...
(02/20/98; 2:30 p.m. EST)
By Anthony Cataldo, EE Times
Intel's plan to maintain hegemony in high-end desktop platforms while extending its reach into low-end PCs came into sharper focus this week at the Intel Developer Forum, where the company unveiled a far-reaching plan to prepare the hardware and software community for its next-generation IA-32 Katmai processor next year and provided more detail about its low-end Covington processor.
The Katmai processor marks a monumental effort that will involve the convergence of new chip sets,
DRAM technology, a graphics bus, MMX instruction set, graphics components, and perhaps a faster system bus. At the same time, Intel has stepped up efforts to ensure a base of software tools and applications that will take advantage of the revamped graphics subsystem.
"There's a tremendous amount of work with how the CPU will interact with memory, chip set, and graphics devices," said Jonathan Khazam, marketing director for graphics programs at Intel in Santa Clara, Calif. "We must get the most value out of every single component on that platform. And we've got a number of different programs in place with software developers in terms of how to best structure their code to take full advantage of the platform."
Katmai itself will be a P6 derivative that will initially be produced on a 0.25-micron process. It is expected to provide up to 512 kilobytes of Level 2 cache. Intel isn't describing details of the processor architecture, but analysts expect that it will stick with a 64-bit CPU bus and rely on deeper pipelining capabilities to take advantage of wider buses and encourage the use of multiprocessing systems.
Katmai will come with 70 new single-instruction, multiple-data (SIMD) floating-point instructions to accelerate 3-D processing. Intel's current MMX instruction set is based on SIMD integer data types. While useful for presenting certain audio, video, and 2-D images, they provide less precision and range for 3-D geometry processing.
Intel is working with the Powersoft Business Group of Sybase in Emeryville, Calif., to provide specialized software tools that will bridge the gap between low- and high-level programming languages for the new instructions. "SIMD was really easy to add to the structure, and it's well understood by people doing 3-D geometry," Khazam said. "The biggest challenge with SIMD is there's not a lot of compilers. Almost everything has to be done in assembly language. And I don't anticipate we'll see compilers, so what we're doing is providing intrinsics, which are at a higher level than assembly language. It's not something as high as C, but it removes some of the hardware details."
Dean McCarron, a principal analyst with Mercury Research in Scottsdale, Ariz., said Intel won't have to worry much about getting base-level support at the OS level, because Microsoft has agreed to support a common set of multimedia instructions from X86 clone makers Advanced Micro Devices, Cyrix, and Centaur that differ from those used in Katmai. "If Microsoft handles both instruction sets through DirectX, it puts [Intel's competitors] on a level playing field," McCarron said.
All told, Intel's Katmai software development program is triple the size of its MMX program, and the company has signed on more than 200 tool and applications vendors since last year.
Graphics performance should get a second jolt by way of the 4X Accelerated Graphics Port (AGP), which will increase the available bandwidth between the graphics controller and main memory from 528 megabytes per second to 1 gigabyte per second. Targeted at workstations and servers, the new specification will provide a "fast write" scheme that allows the CPU to directly access the graphics controller and produce lower 1.5-volt signaling, but will require a 110-watt connector -- the specification for which is under development.
By the time Katmai rolls out, Intel expects to be supporting 800-megahertz, 64-megabit Direct RDRAM, which is scheduled to start shipping in volume in early 1999. Intel has worked closely with Rambus and DRAM vendors for more than a year to coordinate the transition to the Rambus memory. But the high price premium for the newer protocol-based DRAM recently forced Intel to adopt a new module format that could accomodate both Direct RDRAM and 100-MHz SDRAM. Even so, Intel said it still plans to introduce a chip set that will support Direct RDRAM in 1999.
Intel and Rambus officials said that aggressive cost reductions by DRAM vendors have pushed the relative die cost for the initial 64-megabit Direct Rambus DRAM to 10 percent or more compared to PC/100 SDRAM, which is scheduled to roll out in the second quarter of this year. That price difference should fall to 5 percent by second half of 1999, when DRAM vendors start to ship 128-Mbit Direct RDRAM, said David Mooring, vice president and general manager of the personal computing division at Rambus in Mountain View, Calif.
To ease the transition, Intel confirmed that it will provide a specification for a Rambus in-nine memory module (RIMM) that can be populated with SDRAM by using a $3 to $7 transceiver chip. "This is not an interim solution on the way to Rambus, this is a way to accelerate the transition to the RIMM socket on a PC," said Pete MacWilliams, an Intel fellow and director of platform architecture for the Intel Architecture Labs. "We hope to limit the number of different motherboards needed for the PC," he said.
Intel also acknowledged that it is discussing the possibility of including a 133-MHz SDRAM specification in its product road map, but that there has been no final decision on the matter. The company also reiterated that it has no plan to support either double-data-rate SDRAM or SL-DRAM. "We're quite concerned that we'll have too many options and too many components," MacWilliams said.
Besides having hooks to Rambus, Intel's core logic for 1999 -- rumored to be code-named Camino -- is also expected to roll in support for 4X AGP, which would give OEMs a strong incentive to upgrade their high-end systems. "This is going to be so loaded with goodies that its going to be hard for customers not to want to use it," said Bert McComas, principal of market research firm InQuest in Gilbert, Ariz. "This is the most ambitious chip set project they've ever taken."
Meanwhile, Intel shed more light on its low-cost, cacheless Pentium II derivative processor, dubbed Covington, that it will ship in the late second quarter for systems priced below $1,000. The processor will ship in a single-unit, single-edge processor package, and in bulk pack boxes with a clipped-on fan heat sink and a single-metal clip.
The company will also provide a stripped-down version of the 440LX chip set called 440EX, which will support only two DIMM slots and three PCI slots. The stripped down set will remove support for ECC and dual-processor support.
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Yes, 1999 and 2000 are going to be very interesting years indeed! :-)
I hope we're still laughing on SI at all the shortsighted Paul F's out there. <GGG>
Michael |
