Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: Paul Engel who wrote (48371)	2/21/1998 4:49:00 PM
From: Paul Engel	Read Replies (1) \| Respond to of 186894

Intel Investors - A glimpse into Intel's IA-32 Development Plans " This trend has already led to a proprietary backside cache bus and a cache memory chip inside the Pentium II modules. In the future, as the system bus speeds past 100 MHz, the system bus and core logic may well disappear within the module as well, Yu suggested." Intel may be planning to integrate the ENTIRE chip set into the SEC modules along with the processor and cache. That will probably include the graphics and audio as part of the chip set - and hence, integrated into the SEC module. Interesting possibilities. Paul {===================================} techweb.cmp.com Posted: 3:00 p.m. EST, 2/19/98 Intel technologist hints at future of the IA32 architecture By Ron Wilson SAN JOSE, Calif. -- Albert Yu, senior vice president and general manager at Intel Corp. said on Wednesday that Intel's IA32 microprocessor architecture still had a long future and a lot of performance headroom. Yu, who manages architectural development at the microprocessor giant, said both small changes to the IA32 instruction set and major changes to CPU microarchitecture still lay ahead for the venerable X86 line. Moreover, Yu said he did not foresee a time when the IA32 architecture would not exist side-by-side with Intel's new IA64 architecture. Regarding changes coming to the IA32 realm, Yu cited adjustments such as the new Katmai instructions, which will add single-instruction, multiple-data floating-point capability to the current MMX instruction set. Yu would not comment on microarchitectural developments under way at Intel. But such programs do exist, he said. He said there was still implicit parallelism in most IA32 codes that had not been exploited by existing hardware. He also would not comment on ways to exploit that parallelism to execute more instructions in parallel. But Intel has reportedly been working on techniques involving hardware-assisted switching between multiple program threads, and on IA32 processors with more execution units than are used in the Pentium II. In addition, some of the ideas used in the Merced CPU, such as predicated execution, could in theory be used on IA32 code streams as well, without recompilation. Another theme of IA32 architectural development holds a dire warning for other silicon vendors in the PC arena. Integration is a continuing trend for Intel, he said. It "is driven mostly by technical considerations, but also by the question of what is the right thing to integrate at what time. That can be less easy to decide." The underlying trend, according to Yu, is for all high-speed data flows in a PC to gradually disappear inside Intel-provided modules or chips. This trend has already led to a proprietary backside cache bus and a cache memory chip inside the Pentium II modules. In the future, as the system bus speeds past 100 MHz, the system bus and core logic may well disappear within the module as well, Yu suggested.