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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Petz who wrote (28773)	2/24/1998 3:38:00 PM
From: Bill Jackson	Respond to of 1572689

John, I suspect there is some unavoidable variance and you must put enough space to avoid a worst case situation causing shorts. Open would not occur as you would be dealing with continuous resist fields(unless you had a defect). Make them closer and the chance of shorts goes up. Make them wider and the waster space goes up. What is the variance/repeatability inherent in the steppers?, that is the limiting factor. Do the steppers use some kind of servo aligment technique like servo drives, to position the image just so?, or do they rely on the stepper mechanism?. I suspect they must have some kind of precise positioning mechanism that is non mechanical, possibly fringe counts of some kind of interfereometer or laser time of flight thing? Yes smaller die size allows you to miss the cracks in the sidewalk. However there are always smaller cracks, and more of them, so I can a saddle surface here. Bill

To: Petz who wrote (28773)	2/24/1998 6:05:00 PM
From: Paul Engel	Read Replies (1) \| Respond to of 1572689

Petz - Re:"Does someone on the thread know what minimum spacing is used between "traces" on the metallization layers of an Intel" This varies from layer to layer, depending upon the thickness of a particular metal layer. For Intel's 0.25 micron process, their thinnest layer is the first metal layer - for the highest density interconnect. I believe they use a metal line width of about 0.32 microns and 0.32 micron spacing between lines. The top metal layer, used more for power distribution is thicker and Intel uses 1.25 micron lines and 1.25 micron spaces. Paul