To: Jim Mullens who wrote (195419 ) 8/28/2025 12:58:15 PM From: Jim Mullens 1 RecommendationRecommended By
Respond to TSMC metrics from Copilot- Sales by Customer, Wafers/ month, Dies / wafter , Capacity/ nodeTSMC is a near monopoly in advanced state of the art leading edge semiconductors. TSMC Wafer Sales by Major Customers (2024–2026) Units: Estimated Wafer Shipments (Millions of 12-inch equivalents) Customer 2024 Actual 2025 Forecast 2026 Forecast Apple 3.23M 3.60M 3.85M NVIDIA 1.41M 2.10M 2.50M AMD 0.90M 1.10M 1.25M Qualcomm 0.75M 0.85M 0.95M Broadcom 0.60M 0.70M 0.80M Others 6.01M 7.15M 8.15M Total 12.9M 15.5M 17.5M
Revenue: Estimated Sales (USD Billions) Customer 2024 Actual 2025 Forecast 2026 Forecast Apple $22.5B (25%) $26.5B (24%) $29.5B (22%) NVIDIA $10.1B (11%) $16.5B (15%) $21.0B (16%) AMD $7.0B (8%) $8.5B (7%) $9.5B (7%) Qualcomm $5.8B (6%) $6.5B (5%) $7.0B (5%) Broadcom $4.5B (5%) $5.5B (4%) $6.0B (4%) Others $39.7B (45%) $52.0B (45%) $63.0B (46%) Total $90.1B $115.5B $136.0B
Key Insights Apple remains the largest customer, but its share is gradually declining as AI demand surges.NVIDIA is the fastest-growing customer, driven by explosive demand for H100/Blackwell GPUs and CoWoS packaging.AMD and Broadcom are steady contributors, with AMD gaining share in AI and server markets.Qualcomm is stable, with 3nm smartphone SoCs and modem chips.Others include MediaTek, Intel (outsourced), Sony, Marvell, and automotive clients. Monthly Die Output from TSMC Wafers (25k–35k WPM ) Assumptions Recap Wafer size: 300mm ? ~70,000 mm² usable area Yield: 65–70% Die sizes: Flagship ~130 mm², Mid-tier ~100 mm², Entry ~70 mm² Die Output by Tier (Yield-Adjusted) Tier Die Size Dies/Wafer Yield-Adjusted Total Dies @ 25k WPM Total Dies @ 35k WPM Flagship 130 mm² ~540 ~370–400 ~9.25M–10.0M ~13.8M–14.0M Mid-tier 100 mm² ~700 ~500–525 ~12.5M–13.1M ~17.5M–18.4M Entry/IoT 70 mm² ~1000 ~700–750 ~17.5M–18.75M ~24.5M–26.25M Total — — — ~39.25M–41.85M ~55.8M–58.65M
Estimated SoC Output by Tier (Assuming Wafer Allocation) Tier % of Wafers SoCs @ 25k WPM SoCs @ 35k WPM Flagship 30% ~2.78M–3.0M ~4.14M–4.2M Mid-tier 50% ~6.25M–6.55M ~8.75M–9.2M Entry/IoT 20% ~3.5M–3.75M ~4.9M–5.25M Total 100% ~12.5M–13.3M ~17.8M–18.65M
These totals reflect packaged SoCs ready for integration, assuming binning and test pass rates are consistent with TSMC norms.Leading-Edge Capacity by Node and Fab Company (2022–2027) Unit: Thousand 12-inch Wafers per Month (WSPM) Sources : SemiAnalysis, Counterpoint, SEMI, Z2Data, UltraFacility Portal?? 7nm / N7 / Intel 10nm Equivalent Company 2022 2023 2024 2025 2026 2027 Total TSMC 250 270 280 290 290 285 1,665 Samsung 80 85 90 90 85 80 510 Intel — 10 40 80 100 120 350 SMIC 10 15 20 25 30 30 140 Node Total 340 380 430 485 505 515 2,655
... 5nm / N5 / Intel 7 Equivalent Company 2022 2023 2024 2025 2026 2027 Total TSMC 120 180 220 240 250 250 1,260 Samsung 60 80 100 110 120 120 590 Node Total 180 260 320 350 370 370 1,850
... 3nm / N3 / Intel 4 Equivalent Company 2022 2023 2024 2025 2026 2027 Total TSMC — 20 60 120 180 220 600 Samsung — 10 30 60 90 110 300 Intel — — — 10 40 80 130 Node Total 0 30 90 190 310 410 1,030
... 2nm / Intel 20A / Rapidus (Japan) Company 2022 2023 2024 2025 2026 2027 Total TSMC — — — 20 60 130 210 Intel — — — — 10 40 50 Rapidus — — — — — 10 10 Node Total 0 0 0 20 70 180 270
... Grand Totals by Company (All Nodes Combined) Company 2022 2023 2024 2025 2026 2027 Total TSMC 370 470 560 670 780 885 3,735 Samsung 140 175 220 260 295 310 1,400 Intel — 10 40 100 190 240 530 SMIC 10 15 20 25 30 30 140 Rapidus — — — — — 10 10 Overall Total 520 670 840 1,045 1,255 1,475 5,805
