Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: StockMan who wrote (28822)	2/25/1998 4:01:00 PM
From: Jim McMannis	Read Replies (1) \| Respond to of 1573092

Stockman, "covington is a stop gap solution" This is scary, either you are reading my notes on the Intel thread or we are thinking along the same limes. Scary. <G> www4.techstocks.com Jim

To: StockMan who wrote (28822)	2/25/1998 4:07:00 PM
From: AK2004	Read Replies (1) \| Respond to of 1573092

Stockman RE it would be about 10% slower that is a joke. Slower than what, XT? What benchmarks? Intel is famous for hyping its chips. They lost in court because of that recently

To: StockMan who wrote (28822)	2/25/1998 4:47:00 PM
From: Maxwell	Read Replies (1) \| Respond to of 1573092

Stockman: <<For starters covington is a stop gap solution for 3 months before mendocino (which has L2 cache on chip). Also Intel has said that it would be about 10% slower, and its believable because with AGP, ultraDMA, and 266Mhz .>> So what? Socket 7 has AGP, 100MHz bus speed, and ultraDMA, and a BIG L2 CACHE. A Castrated PII has NO DIB (dual independent bus). It relies everything on system memory which makes it slow as hell. You need to take a course in computer architecture to understand what you are talking about. Let me give you a simple introduction. When a CPU wants to make an execution it goes 1st To the L1 cache to look for the instruction. If it doesn't find 2nd Then a snoop is sent by the CPU to look into the L2 cache. L2 cache is an SRAM that has a response of about 2-4 ns. A SDRAM has a delay time of 10ns. Thus SRAM is 2X to 5X faster than SDRAM. 3rd If the L2 cache doesn't have it then it goes to the chipset and call up the system memory. The system memory runs at system bus speed of 66MHz-100MHz. The memory then start to transfer the data to the CPU and the L2. Intel opt to bypass the 2nd stage which will SIGNIFICANTLY reduce the system performance. Even if INTEL improves the Castrated Covington by 2 fold the system is STILL LIMITED by how fast data can transfer from system memory to the CPU. So get lost to the mountain to learn your basic. Maxwell