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To: Barry A. Watzman who wrote (48845)	2/25/1998 11:21:00 PM
From: Elmer	Read Replies (1) \| Respond to of 186894

<Slot 2 will use memory running at full CPU speed, which will be VERY expensive, and the processor will have to run at a multiple of the clock speed, which will be 100 MHz, so it won't be a 233, it would have to be a 200, 250, 300 or 350. (the clock to CPU ratios so far have been at multiples of 0.5).> Barry, I believe you have this wrong. It is the Cache that will run at full core speed, not the memory, or perhaps you just mispoke and meant Cache memory. Which ever, I believe your statement that the core must run at a even 1/2 (200, 250, 300 350 etc) multiple is also wrong. <while a socket 7 device accesses cache at the PCI bus speed. > No. Cache does not reside on the PCI bus. For a socket7 device, it is accessed at the processor bus speed, currently 66mhz, and 100mhz at some future date. EP

To: Barry A. Watzman who wrote (48845)	2/26/1998 3:53:00 AM
From: Paul Engel	Respond to of 186894

Barry - Re: "Paul, do I have this mostly right ?" Most of it is right except:" a socket 7 device accesses cache at the PCI bus speed. " A Socket 7 CPU will address L2 cache as fast as the external system clock speed will allow. The cache is controlled by the chip set and neither sits on the PCI bus. (PCI bus speeds currently run at only 33 MHz). Also - Re: "and: "Slot 2 will use memory running at full CPU speed" The on board L2 cache will be accessed at full CPU speed for Slot 2 devices. Paul