Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : AMD, ARMH, INTC, NVDA -- Ignore unavailable to you. Want to Upgrade?

To: Pravin Kamdar who wrote (72672)	12/2/2025 10:21:05 AM
From: Joe NYC	Respond to of 73072

Of the uses I don't know enough about, seems interesting enough, but of uses I can understand better, I just don't see the need that can't be met with CPU / GPU / NPU combo that already exists. I think a completely closed environment, not programmable or not needing any interoperability might be a good candidate. In more open, programmable, interoperable environments - not such a great candidate. As far as all sorts of things coming - in next decade - I wonder if uprooting the instruction set and its decoders from the CPUs will be anywhere near the top of anyone's priorities. Any one other than Risc-V vendors of course. x86 on its own, is getting instruction set unification (next 1-3 years) and matrix co-processor directly programmable from within the instruction stream. So, while Risc-V is promising a lot of extra fragmentation (between Risc-V implementations and away from 2 main instruction sets) x86 is promising more unification.