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Technology Stocks : ASML Holding NV -- Ignore unavailable to you. Want to Upgrade?

To: BeenRetired who wrote (42700)	12/16/2025 6:59:08 PM
From: BeenRetired	Respond to of 42735

Like ASML lasers, cost/wafer only totally misleading. "Some reports claim that TSMC will be charging $30,000 each for its upcoming N2 wafers, while the price for its even more advanced A16 node could be as high as $45,000 per wafer. TSMC is currently said to demand $18,000 for an N3 wafer, like those used for Intel's Lunar Lake mobile CPU, while back in 2013 it was reportedly charging just $5,000 for a 28 nm wafer." Copilot: 1. Why wafer price alone is misleading You’re exactly right: as nodes shrink, more dies fit on a wafer, and yield improves (after ramp), so the effective cost per CPU or per transistor often continues to fall even when wafer prices explode. A $30k N2 wafer is shocking only if you ignore that: die area shrinks defect density improves design efficiency improves packaging shifts (chiplets) reduce the need for monolithic dies This is why TSMC, Intel, and Samsung still talk about “cost-per-transistor scaling” even though the raw wafer price is skyrocketing. 2. Is cost per CPU known for each new node? Not publicly, not directly. Foundries never publish cost-per-die, and customers never disclose their wafer pricing agreements. But we can estimate it because three variables are knowable: Wafer price (reported or leaked) Die size (from teardown labs like TechInsights) Yield (estimated from defect density trends) For example: A hypothetical N3 CPU die Wafer: ~$18,000 Die size: 120 mm² Dies per wafer: ~500 Yield: ~70% Cost per good die ~ 18,000500·0.7~$51 That’s why even a $999 CPU can still have a die cost of only $40–$80. At N2 or A16, the wafer price goes up, but the die size shrinks, so the cost per CPU doesn’t rise proportionally. 3. Is cost per transistor known? Yes — indirectly. This is the metric TSMC, Intel, and Samsung do publish in their technology roadmaps. This is the “end of Dennard economics” in slow motion. Scaling still helps, but the curve is flattening. 4. Why this parallels ASML’s lasers Your analogy is spot-on. ASML EUV Tool price: skyrocketing Throughput: rising Cost per layer: rising Cost per transistor: falling (because EUV replaces 3–4 DUV multi-patterning steps) TSMC nodes Wafer price: skyrocketing Dies per wafer: rising Yield: improving Cost per transistor: falling (but more slowly each generation) Both industries follow the same physics-driven pattern: Capex explodes, but unit economics improve — until they don’t. 5. The real inflection point We’re approaching a regime where: wafer prices rise faster than die shrink EUV layers increase backside power delivery adds cost GAA transistors add complexity packaging (CoWoS, SoIC) becomes a major cost driver This is why chiplets are now mandatory. Monolithic dies at A16 would be economically insane. Bottom line Cost per wafer is rising dramatically. Cost per die is rising slowly or staying flat. Cost per transistor is still falling, but the slope is flattening. Chiplets and advanced packaging are now the real cost equalizers. Your instinct is correct: the articles that only quote wafer prices are telling half the story. If you want, I can run actual die-per-wafer calculations for any CPU or GPU you’re curious about — Zen 5, Lunar Lake, M3, Blackwell, whatever you want.