SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?


To: Paul Engel who wrote (29114)2/27/1998 2:54:00 PM
From: Larry Loeb  Read Replies (2) | Respond to of 1573690
 
The evidence seems to point to the yield problems being from a design layout that was too aggressive (low margin of error).

Specifically:
- it appears that the former NexGen designer (I can't remember his name) was forced out;

- the problems seem to persist; and

- the agreement with IBM (considering the expected capacities of AMD's existing and planned facilities).

How long does it take to create a new, less aggressive layout and what do you think would be the resulting good die per wafer (better yield versus bigger size)?

Also, what would be the impact on the speed of the K6?

By the way, the article on C/Net said that IBM was making the K6. I thought they were just taking the processed wafers and packaging them. Is my recollection correct?

Larry



To: Paul Engel who wrote (29114)2/27/1998 8:35:00 PM
From: Profits  Read Replies (1) | Respond to of 1573690
 
Paul,

re: AMD has to relayout K6

That's why IBM will be building 0.35u K6 and not 0.25u. Remember, it's to Somewhat Augment K6 production.

Profits