'Asian flu' delays DRAM shifts . . .
Electronic Engineering Times, Friday, February 27, 1998 at 23:20
by Anthony Cataldo
San Jose, Calif. - Girding for a prolonged DRAM depression and deep
cutbacks in capital spending, Asian memory makers are following the
lead of Micron Technology and squeezing costs out of the 16-Mbit
synchronous DRAM even as the crossover to the 64-Mbit device is well
under way.
Meanwhile, Intel Corp. has relaxed the timetable for DRAM vendors to
meet cost parity for Direct Rambus DRAMs while continuing to rule out
the possibility of endorsing other architectures for its forthcoming
"Camino" chip set.
Following a strategy made famous by Micron Technology Inc. (Boise,
Idaho), several top-tier Korean and Japanese semiconductor
manufacturers recently said they plan to cut the cost of producing
16-Mbit SDRAMs by shrinking the size of the die to 0.25-micron line
widths, the same process used to build 64-Mbit devices today. Vendors
and analysts said the move arises from the need to gain some short-term
profits from the 16-Mbit devices as many companies limit their capital
expenditures to process improvements rather than capacity expansions.
Steven Przybylski, principal consultant with the Verdande Group, said
the financial turmoil among Asian chip companies will push the
crossover from 16- to 64-Mbit DRAMs out to the second half of 1998. "If
it wasn't for the Asia crisis, we would have had a price crossover
already," he said.
'Tough to make money'
Indeed, "With the cost of a 16-Mbit device $2.85 to $3 in the spot
market and contract prices at $4 to $5, it's tough to make money," said
Mario Morales, a senior analyst with International Data Corp. (Mountain
View, Calif.). "Micron, however, can get 1,000 die per wafer. Everyone
else is at 750 to 500 using 0.4 or 0.35-micron, so Micron is making
money at those price points right now."
Last September, Micron shrunk the size of its 16-Mbit architecture to
0.3 micron from 0.35, a half step that most DRAM vendors had resisted
in favor of trying to gain market share in the more profitable 64-Mbit
arena. But spot-market prices for the 64-Mbit part have dropped as low
as $15 while the cost of making the device is still around $20. As a
result, vendors see squeezing their 16-Mbit manufacturing costs as a
way to eke out some profits in the short term.
Micron plans to implement its ninth 16-Mbit die shrink sometime this
year, migrating its process to the 0.25-micron technology used today
exclusively for 64-bit DRAMs. A spokeswoman said the company is
uncertain whether to shrink 16-Mbit devices beyond that, considering
that the cost savings are shrinking along with the die sizes.
"We've been upping our 64-Mbit wafer starts in the last few months and
it's now about 25 percent to 30 percent of total wafer starts," she
said. "I think we're coming to the tail end of the 16-Mbit cycle."
Hyundai Electronics will shrink its 16-Mbit SDRAM die from a
0.32-micron process to 0.28-micron in the third quarter. "More DRAM
companies are putting emphasis on upgrading fabs rather than adding
capacity. The 64-Mbit needs a 0.25-micron process to be cost-effective,
but at the same time we still have capacity for 0.28-micron. And we
need to make money," said Farhad Tabrizi, director of strategic
marketing for Hyundai Electronics America (San Jose). "I think we have
all learned to lean toward smaller die sizes. Maybe Micron has provided
a good lesson to the industry."
Toshiba said it will also shrink its 16-Mbit synchronous devices from
0.45-micron design rules to the 0.25-micron process used on its
second-generation 64-Mbit SDRAM. Reductions beyond that are in doubt,
said Kevin Kilbuck, technical-marketing manager for Toshiba America
Electronic Components Inc. (Irvine, Calif.).
"We're going to have to decide what if anything to do after that with
the 16-meg," he said. "Some applications don't need the higher density,
such as low-end PCs or set-top boxes. But we get more bits per wafer
for the 64-Mbit part, and we think that most of the demand going
forward is for 64-Mbyte DIMMs [dual in-line memory modules]."
At the same time, Intel and Rambus officials said that aggressive cost
reduction by DRAM companies has pushed up the relative die cost for the
initial 64-Mbit Direct Rambus DRAMs to 10 percent or higher than PC/100
SDRAMs, which are scheduled to roll out in the second quarter. That
price difference should fall to 5 percent by the second half of 1999,
when DRAM vendors start to ship 128-Mbit Direct RDRAMs, said David
Mooring, vice president and general manager of the personal computing
division at Rambus Inc. (Mountain View, Calif.).
"In the last six months, we've seen DRAM pressure continue and forces
leading to instability in the DRAM community," said Pete MacWilliams,
Intel fellow and director of platform architecture for Intel
Architecture Labs (Hillsboro, Ore.). Speaking to a gathering of
hardware developers, MacWilliams said, "All this leads to an
uncertainty, and it also means transitions are more difficult and being
able to invest in new capital becomes difficult." Still, Intel sees "no
fundamental change" in its road map, he said.
Interface delivered
Mooring of Rambus said PC OEMs will still have a compelling reason to
move to 64-Mbit Direct RDRAMs in 1999-when Intel plans to introduce a
chip set that supports the new architecture-because it will offer three
times the bandwidth of SDRAMs. Rambus last week delivered its Direct
RDRAM interface circuit design to its 13 partners, and at least nine
DRAM companies indicated they will begin sampling the device this year,
some by next quarter.
Intel confirmed it will provide a specification for a Rambus In-Line
Memory Module (RIMM) that can be populated with SDRAMs by using a $3 to
$7 transceiver chip. "This is not an interim solution; this is a way to
accelerate the transition to the RIMM socket on a PC," said
MacWilliams. "We hope to limit the number of different motherboards
needed for the PC."
Intel also acknowledged that it is discussing the possibility of
including a 133-MHz SDRAM specification in the road map, but said there
has been no final decision. Intel reiterated that it has no plan to
support either double-data-rate SDRAMs or SL-DRAMs. "We're quite
concerned that we'll have too many options and too many components,"
MacWilliams said.
Copyright c 1998 CMP Media Inc. |
