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To: Darrell D. Conrade who wrote (7057)3/1/1998 4:19:00 PM
From: Rob S.  Respond to of 11555
 
PC hardware has gotten more powerful over the years because of advances in uP power - cramming more and more "transistor equivalent circuits" on a given size piece of silicon. The motherboards (MB) that these and the support chips go into have tried to keep up with the uP chips by increasing the frequency (speed) and bandwidth (number of lanes of traffic) of information that travels between each component or subsystem, such as the uP and the graphics & sound cards and disk controllers. The PCI bus used in most systems today increased the bandwidth but was limited in frequency. The sockets that are used to plug processors into the motherboards have also increased in number of pins (bandwidth) and frequency capability. The socket 7 MB architecure and PII PCI bus has been extended to 60 Mhz for Pentium chips and to 75 Mhz for boards that support Cyrix processors. AMD, Cyrix and IDTI are supporting "Super Socket 7" which will extend the MB frequency further to 100 Mhz. Increasing to this frequency is a difficult task. All the components used in the system that fit on the bus are being stressed to very tight timing requirements. At the higher frequencies, short circuit traces on the motherboard look increasingly distant in terms of controlling the timing of when signals get to where they need to go. What's called "reactances", the inductance and capacitance of the traces and component interconnects, look increasingly like detours or roadblocks to the travel of information. Some of these roadblocks are due to the nature of the materials used in circuit boards - the glass epoxy MB and copper traces are good to fabricate complex circuits but are less than ideal from the standpoint of limiting the reactances that create traffic problems. One way to reduce the problems is to pack components closer together. But thats difficult to do using traditional MBs. Intel saw that at some point the problems of trying to increase MB frequency would become counter-productive in terms of manufcturing cost and complexity. One solution to the overal roadblock in ramping speed is to put chip components onto materials that have better transmission properties (lower reactances and finer trace lines) and can be packed closer together than conventional MB materials. An approach that has been used extensively starting with military/aerospace applications is called "multichip modules". Of course for those applications cost was hardly ever the defining requirement. So when Intel was confronted with the entry of AMD and Cyrix as worthy competitors, they shifted the MB design toward the new slot 1 and soon slot 2 designs that use a commericalized version of the multi-chip modules approach. Slot 1 or similar designs that may evolve, mount the uP and SRAM onto a substrate material that has better conductive properties and on which the parts can be packed closer together. This reduces the bottlenecks between the components on the slot card. You still face similar limitations when you go from the slot connector on the MB to other components.

Many people consider Intel's use of slot 1 as being "before its time" and at least partly as a strategic ploy to fend off competition. Intel patented certain aspects of the design. Because Intel holds the vast majority of PC marketshare, it doesn't much matter that their patent can be easily gotten around with another design - if it's not exactly compatible to slot 1, it won't fly in the marketplace.

To counter that move, AMD, Cyrix, IDTI and a host of chip-set and MB mfgs. have developed the 100 Mhz "super socket 7". Super socket 7 will still use the same basic design of current socket 7 MBs in which SRAM and other support components are mounted on the MB or put into PCI slots or memory sockets. But the performance achieved will be about equal to more expensive PII slot 1 systems.

Another way to increase speed between PC susbsystems is to cram the stuff onto the same piece of silicon as the uP and/or system logic and pack it closer together on the MB or multi-chip slot module. Cyrix did this in the MediaGX parts to turn an otherwise out of date core uP design into a worthy competitor for low cost systems. Here they packed audio, video, memory management, I/O and other functions into two pieces of silicon. The next generation of uPs; C6+, K6 3D, and M2+, will do some of this by putting 3D graphics capability combined with larger on-chip cache memories onto the uP chips. NSM has announced plans to develop "systems on a chip" parts for release early next year. All these efforts are attempts to get around the the current performance plateau and revitalize the growth in PC performance while reducing overal system cost.

Socket 7 will probably be around for another 18 months before other architectures become necessary. It will likely be around well past that for lower end systems. AMD is working on a slot like architecture using licensed DEC interface technology that is said to be superior to Intel's slot 1. IDTI and Cyrix can piggy back that effort if AMD allows it to become an open standard.

Success of one architecture or another has as much to do with marketing and production clout as it does with technical advantages. Intel thought that the market could be moved away from socket 7 and over to slot 1. The problem has been that slot 1 is a more expensive approach - both to build module and the motherboard. That differential has been emphasized by the tremendous growth of the sub $1000 market.

Hope this helps a bit.