Good Morning Paul and everyone, Article...A New PC World Order...
March 3, 1998
Electronic Engineering Times via NewsEdge Corporation : As Intel prepares to replace its aging 32-bit architecture with the highly parallel, 64-bit Merced microprocessor, the PC world is poised for an upheaval. Though Merced isn't expected to ship for another two to three years, Intel's competitors are already looking to take advantage of the marked discontinuity the transition from 32 to 64 bits will wreak. The result will be a PC market filled with silicon alternatives. Believing there's ample life in the 32-bit world, some of Intel's competitors are launching low-cost, 32-bit clones. New players in this market include startups Centaur Technology Inc. (Austin, Texas) and Transmeta Corp. (Santa Clara, Calif.)
Other venerable suppliers of PC microprocessors are working hard to forge next- generation 64-bit chips of their own, even as they continue to be major players in the existing 32-bit world. Here, Intel itself and archrival Advanced Micro Devices Inc. (Sunnyvale, Calif.) are expected to dominate in the design of desktop-ready CPUs.
Perhaps the most interesting trend spawned by the coming bifurcation into 32- and 64-bit markets is the creation of a new low end in the 32-bit world. Centaur, founded by renowned microprocessor architect Glenn Henry, is focusing there, on the portion of the market where sub-$1,000 desktop machines and sub- $2,000 notebooks rule. Its offering, launched only a few months ago, is called the IDT WinChip C6 ("IDT" stands for Integrated Device Technology Inc., which owns Centaur). This Pentium-class processor supports the MMX multimedia instruction-set extensions, a Socket-7 interface and comes in speed grades of 180 and 200 MHz. Centaur is positioning the C6 as a direct alternative to In- tel's Pentium with MMX, AMD's K6 and Cyrix Corp.'s 6x86MX microprocessors.
From a design standpoint, what's interesting about the C6 is that Henry chose not to follow the reigning trends in chip architecture. Instead, he took a downsized approach, implementing just those features he needed to deliver decent performance in a high-volume, low-cost CPU.
"The biggest thing we did is throw out conventional thinking," Henry said. "We came to the conclusion that the added benefit of a lot of computer-science things wasn't worth the effort. We're not superscalar-we don't do out-of-order execution. Everyone else is designing four-way superscalar processors, so we did a six-way chip."
Henry said his team found that, as CPU clock speeds approach 200 MHz, nearly half the time is spent waiting on the bus. So Henry outfitted the C6 with a huge translation-lookaside buffer, as well as a second-level TLB, to reduce bus utilization and cut that wait time to the bone.
Also notable is the fact that Centaur is a tiny outfit that began life a scant two years ago. "Intel would like the world to believe it takes tens of years and dozens of people to design a microprocessor," Henry said. Looking at the results rolling out of Centaur, it's obvious what a dedicated group of engineers can do in very little time.
Over at AMD, a somewhat larger engineering team is already burning the midnight oil to design the K7 (code-named "Argon"), which will compete with Intel's 64- bit Merced. To date, few details on the chip have emerged. Nevertheless, experts agree that the K7 will be the key to AMD's long-term prospects.
Recently, AMD chairman Jerry Sanders reported that the K7 will run at clock speeds in excess of 500 MHz and will come in a module that's mechanically-though not electrically-interchangeable with Intel's Slot 1 connector. Most interesting is the news that K7 will use the bus protocol developed by Digital Equipment Corp. for its Alpha EV-6 processor.
The third, and potentially most interesting, effort involves Transmeta, a startup formed less than three years ago by former Sun Microsystems Inc. chip architect David Ditzel. Initial word had Transmeta at work on a PowerPC clone. Then, the buzz had the company designing a Java chip aimed at the nascent market for low-cost network computers. Now, it seems Transmeta's effort is focused more on an X86 alternative that boasts either low-power, multimedia or network- computer capabilities.
While Intel's competitors ready exciting new silicon, Intel itself is forging a new PC world order with its innovative 64-bit architecture and companion Merced microprocessor.
Intel has dubbed its approach "explicit parallelism." It relies on a new kind of cooperation between the hardware and the compiler in its IA-64 architecture. (Hewlett-Packard Co. worked with Intel to define the instruction set used in IA- 64.)
To date, the fundamental tool for keeping the execution units humming in a microprocessor has been to maintain a pool of ready instructions and dispatch as many as possible on the next clock. The problem, according to architects, is that conventional programs usually don't make enough instructions ready at any one time for the CPU to dispatch more than a couple in an average cycle.
To up the ante, Intel intends to create a machine that can take a large number of instructions and feed them to functional units on every clock cycle. That is, Merced hardware will contain a variety of execution units. The companion compiler will organize instructions into simultaneously executable blocks, and give the hardware important assistance in avoiding memory latency and skipping over branches.
At the heart of the IA-64 architecture lie the dual bulwarks of predication and speculation. The former is intended to remove branches from code, while the latter masks the problem of memory latency.
In practice, predication removes branches from code by essentially executing both pre- and post-branch instructions at the same time. Then, the results from instructions that wouldn't have been executing during a real-world sequential run through the code are thrown out.
Speculation, the second technique, essentially yanks load instructions out of their normal place in the middle of a branch, bringing them forward to be initiated as early as possible in the program flow. Although that doesn't change the actual latency involved in accessing memory, it masks the problem, since the accesses in question are performed well in advance of when they're needed.
Despite the heady opportunities for designs built around Intel-architecture CPUs, some vendors are sticking firmly to alternatives. The biggest case in point is Sun Microsystems, which recently cut off at the knees industry speculation about a possible long-term tilt toward Intel's 64-bit Merced architecture.
Indeed, Sun emphatically insists it will stick with its Sparc RISC processor family now and in the future. Moreover, Sun said it remains committed to Unix and won't move to the increasingly popular Windows NT operating system-something many of its workstation competitors have done.
But Sun is in the forefront of a new world order of its own, one that could have a profound effect on desktop computing. Sun's microelectronics subsidiary is paving the way for a generation of Java-specific microprocessors-dubbed picoJava, microJava and ultraJava-which will begin to hit the market in 1998.
The first out will be picoJava processors made and marketed by semiconductor licensees. These include Fujitsu, LG Semicon, NEC, Rockwell and Siemens. (Patriot Scientific is also fielding its own Java processor.) The chips will contain the picoJava core plus input/output and memory-access capabilities that will create a fully integrated microprocessor.
The question of just how well the CPUs will do in the market will depend on whether they can deliver heavy-duty performance. So far, some Java observers are skeptical.
Sun is working hard to address their qualms. In picoJava, which is aimed at the embedded market, Sun is addressing performance by including a hardware Java Virtual Machine that lets Java byte codes execute directly without passing through an interpreter. The hardware JVM is expected to deliver performance at or slightly better than a just-in-time compiler. For example, if invoking a method in Java would take a few hundred instructions in a software interpreter, it might take 10 to 20 microinstructions in the hardware JVM.
To facilitate embedded applications, picoJava is being outfitted with extra instructions-called extended byte codes-not found in the standard Java instruction set. The extended byte codes correlate directly to low-level chip- control operations such as register accesses, cache control and load-and-store operations.
In practical use, the extended byte codes are supposed to make it easier to control modems and network-interface devices. To up performance, they can be executed directly by picoJava in the same way that it handles the standard Java instructions.
The hardware JVM and extended byte codes will also be included in microJava, which is positioned as a CPU for network computers.
However, a different architectural tack is being taken with ultraJava, the high- end processor intended to power workstations. According to informed sources, this chip will utilize a hybrid approach that incorporates the hardware-JVM technology along with characteristics of a conventional RISC processor.
Sun engineers are reportedly still working to nail down implementation specifics. In addition, software executing on ultraJava will be augmented by Hot Spot, a vaunted new optimization technology that Sun unveiled in 1997. But it's still unclear whether Hot Spot will be used as a software adjunct or incorporated directly into the processor's JVM.
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Regards, Michael |
