This may be of use to Clay Douglas and our engineers:
I don't know what any of this gibberish means but nevertheless here it is....
Copyright 1993 PennWell Publishing Company ÿ
Solid State Technology
August, 1993
: Vol. 36 ; No. 8 ; Pg. 29; ISSN: 0038-111X
Plasma etching charge-up damage to thin oxides.
Hyungcheol Shin ; Jha, Neeta ; Qian Xue-Yu ; Hills, Graham W. ; Chenming Hu
ÿÿÿMOS gate oxide degradation has been attributed to electrical charging during plasma processing (1)-(23). Since plasma-induced damage may cause further IC yield loss by enhancing the oxide's vulnerability to hot-carrier-induced degradation and time-dependent dielectric breakdown (TDDB), the issue of plasma-induced degradation is a critical one for VLSI processing.
In a plasma ambient, charge is collected on metal or polysilicon electrodes, often called "antennas ". The resultant current flow causes current-induced stress and can lead to charge trapping in the oxide and trap generation at the Si(O.sub.2)-Si interface. Interestingly, these very phenomena may be used to measure the oxide-charging current. Interface trap density ((N.sub.it)) and oxide-charging current can be determined from CV and MOSFET characteristics such as the subthreshold swing, threshold voltage ((V.sub.T)), or mobility (24).
Polysilicon-gate MOS capacitor test structures were fabricated on 4-in. diam. n-type (100) silicon substrates with gate oxides grown in dry oxygen at 900 (degrees) C. The aluminum was photolithographically defined and etched using C(l.sub.2) gas in a parallel plate plasma system. Photoresist was stripped using (O.sub.2) in a barrel plasma asher. To characterize oxide damage produced by plasma processing, changes in both ramp breakdown voltages (V.sub.BD) and quasistatic CV curves were measured after each process step, and results were compared with those obtained from control wafers that had been wet etched and stripped.
Is the plasma stress ac or dc?
During rf plasma processing, the surface of the wafer intercepts a plasma conduction current that has a steady ion and a pulsed electron component (25). If the ion and electron currents were in perfect local balance over the rf cycle, precise recombination of opposing charges would occur on each gate, and there would be no net current flow. Assuming an ion current density (J.sub.i) of 10 pA/((micro)meter.sup.2)(10), an oxide thickness of 10 nm, an rf excitation frequency of 13.56 MHz, and an antenna/thin-oxide area ratio (antenna ratio) of 1000, the maximum gate voltage excursion in 1 rf cycle will be less than
(Mathematical Expression Omitted)
where (Delta)(V.sub.g) is the maximum voltage on the gate and (C.sub.ox) is the oxide capacitance per unit area.
But when the ion and electron currents are not in local balance throughout the rf cycle (12), charging occurs. In this case the gate voltage increases or decreases over an rf cycle, depending on which carrier current is larger, until a steady state oxide voltage is reached. At this point the Fowler-Nordheim tunneling current through the oxide balances the net current collected by the antenna.
If we assume a time-average electron current density (is less than)(J.sub.e)(is greater than) of -8 pA/((micro)meter. sup.2), then the time (t.sub.charging) to reach steady state at (V.sub.g) = 10 volts is approximately
(Mathematical Expression Omitted)
At steady state, the gate voltage remains nearly constant with only a small-amplitude, superimposed 13.56-MHz ripple, similar to the effect calculated with Eq. (1). Plasma charging can, therefore, be approximated as a dc stress to the oxide. A study of plasma transients during turn-on and turn-off found no stress effects associated with the transients, and they probably have little effect on oxide charging if their duration is 1 msec or less (26).
Extracting the oxide-charging current from interface traps
Figure 2 shows quasistatic CV curves for MOS capacitors following plasma etching of aluminum pads of different sizes (static pad capacitances have been subtracted). Deformation of the CV curves is clearly evident. The CV characteristics of capacitors with larger pads show more degradation because larger aluminum pads collect more charging current during etching (antenna effect). It is well known that while breakdown may not occur until about 10 C/(cm.sup.2) of charge has passed through the oxide, interface traps are detectable even after 0.001 C/(cm.sup.2) of charge passage. Clearly then, measuring interface traps is a much more sensitive means of evaluating equipment, monitoring and developing processes, and quantitatively studying charging mechanisms.
If plasma-induced damage is, in fact, dominated by current stress, then process damage to the gate oxide should be similar to that produced by applying a constant current to the gate electrode. Such a test current would correspond to the average current collected by the antenna pads during plasma etching. In Fig. 3, CV curves of wet etched capacitors were identical independent of the antenna ratio and location across a wafer. These wet-processed antenna structures were stressed using a constant current through the gate. Following this, the reference curves shown in Fig. 3 were generated. The CV curve of a plasma-etched 16,000 ((micro)meter.sub.2) aluminum pad capacitor is also shown for comparison. It matches the 10-nA reference curve well, indicating that the 16,000 ((micro)meter.sub.2) Al plasma sample also collected an average of 10 nA charging current during etching. By using this procedure, an effective plasma charging current (called the stress charge, i.e., the product of the charging current and the stress time) can be deduced for each test capacitor. If wet etched control capacitors are not available, then a device with a very low antenna ratio can be used for the control (the assumption being that the low ratio device suffers negligible damage).
Charging current distribution
Figure 4 shows quasistatic CV curves for MOS capacitors at five locations across a wafer following aluminum plasma etching (19). Curves for wet-etched capacitors (curve F) were identical at all positions, whereas a radial variation in stress is observed with greater degradation near the center of the wafer for plasma-etched samples.
Two causes for this charging distribution are probable: radial distribution in the plasma current flux and variation in radial etch rate. Since oxide is mostly stressed after the Al has been etched into isolated patterns, devices near the slower etching region spend less time under stress. Figure 5 plots a distribution of effective oxide-charging current across a wafer. Such spatial patterns are hard to determine from oxide breakdown data because the latter become confounded with the random distribution of oxide defects.
Enhanced etching
MERIE and ECR etching have been introduced as alternatives to conventional plasma methods. Reactors for both produce higher plasma densities with lower ion energy. Contours of the equivalent oxide-charging current across a wafer in a static-field MERIE reactor (21) are shown in Fig. 6. (In normal operation, the magnetic field in a MERIE etcher is rotated at 30 rpm or more to improve etch rate uniformity). About half the wafer was subjected to positive average current flow, while the remainder collected negative current. Namura et al. found a similar distribution in the threshold voltage change of EEPROM test devices processed with static field MERIE (22).
When the static magnetic field is perpendicular to the electric-plasma sheath field, secondary electrons emitted from the wafer surface will tend to move in a cycloidal motion toward one side of the wafer, thereby enhancing the ionization process and increasing the plasma density in the zone marked X. One plausible model of the current path during static MERIE suggests that current flows from the dense plasma region into the antennas, down through the oxide, into the silicon substrate, and up through other oxide and antenna structures into the weak plasma region. When the magnetic field rotates, more charging occurs around the wafer edge since the charging current for the static field case is very small near the wafer center regardless of the magnetic field direction.
One may speculate that in plasma etching without magnetic enhancement, current flows from the plasma to the antenna and through oxides near the wafer center, while around the wafer edge, the flow is out of the oxides and the antenna into the plasma. An alternative current path is from the plasma into the antenna, through the oxide, the substrate, the substrate holder, and the leaky coupling capacitor into the rf generator. However, no experimental proof exists for these assumed current paths.
Effect of photoresist on plasma charging of oxide
To better understand the effect of plasma processes on thin oxides and the Si(O.sub.2)-Si interface, one would like to know what part of an antenna pad collects current during etching.
In Fig. 8, the effective stress current during Al etching is shown as a function of Al pad peripheral length. Since the slope of the line representing normal aluminum etching is about 1, we conclude that the stress-producing current is proportional to the peripheral length of the pads. We further conclude that only the part of the Al surface that is exposed to the plasma during etching (i.e., the perimeter) collects current during the process. An additional test of this hypothesis occurs during plasma etching, where blanket photoresist remains over Al pads that have been previously patterned by wet etching. In this case, the effective oxide-charging current (as measured by CV shift) was negligible, suggesting that the photoresist (KT1820) blocked charge collection from the plasma.
With dry photoresist stripping, in contrast to Al pad etching, the entire wafer surface is exposed to the reactive environment during the overetching (ashing) step. In this case, charging current that is present is thus proportional to the pad area and, consequently, in-plasma ashing is potentially a more damaging process. Fortunately, there is no need for stripping to be anisotropic, and the process can be carried out in a charge-free afterglow.
How does charge-up depend on process?
The process dependence of charge-up has been characterized by varying the magnetic field, pressure, chemistry, and time. MOS polysilicon gate capacitors with 11-nm gate oxides fabricated on 6-in., p-type substrates were used to investigate charge-up in a MERIE polysilicon etcher. Large-area capacitors (up to 10 (mm.sup.2)) and large antenna capacitors (antenna ratios up to 100,000:1) were tested with photoresist both on and off. Photoresist-on is the normal situation for polysilicon etching. Without photoresist, the test structures are exposed to the plasma after polysilicon etch and wet resist strip--a much more stringent test that exaggerates the plasma-induced charge-up effects (27, 28). Gate oxide integrity was measured using ramp breakdown, leakage current, and charge-to-breakdown, (Q.sub.BD). Quasistatic CV measurements were also made for samples etched in rotating and static magnetic fields.
With photoresist-on, different process conditions produce no significant charge-up. Since only the sidewalls are exposed to the plasma during and after clearing, the charge buildup is insufficient to impact (V.sub.BD), ( Q.sub.BD), or (V.sub.T) shift (27). Without photoresist, however, the effect of different process variables is magnified and can be seen by all the measurement techniques used here (27,28). Charge-up stress current increases with increasing nonuniformity in the plasma density and is maximum at the wafer edge. At constant magnetic field, decreasing pressure increases magnetic enhancement that produces greater charge-up. Plasma etching chemistry also plays a significant role in charge-up; (SF.sub.6) etching produces the highest values and manifests the greatest ion density gradient.
Large-antenna, small-area capacitors are simpler test structures for charge-up evaluation, as their percentage failures show a linear relationship with the stress current. The gate failure percentage for the large area capacitors is determined by the random defect distribution. All the measurement techniques show similar trends with respect to magnetic field, pressure, and time (27). However, the effects of chemistry are distinct. For example, charge-up distributions across the wafers are very different for the He/(O.sub.2) chemistry (28).
Oxide thickness dependence of damage
Figure 9 shows effective oxide charging current with corresponding oxide voltage (and oxide field) for three different gate oxide thicknesses. Charging current was determined by the (D.sub.it) method. The gate voltage and its corresponding field were determined from measured I-V relationships that followed the Fowler-Nordheim tunnelling current theory very well.
The measured effective charging current varied over two orders of magnitude while the oxide field variation was only 30%. These data suggest that the plasma acts more like a constant current source than a constant voltage source, a phenomenon that augers well for the future of thin oxide devices.
It is useful to consider why charging current depends at all on oxide thickness. Since the electron current entering the oxide is an exponential function of gate voltage, the plasma charging current (I.sub.p) can be expressed by the Langmuir probe I-V characteristics as (29)
(I.sub.p) = (I.sub.i) - (I.sub.e0) exp q(V.sub.s)/k(T.sub.e) (3)
where (I.sub.e0) is the magnitude of the electron current at (V. sub.g) = 0. With the gate charging voltage, (V.sub.g), smaller for thinner oxides, the second term is smaller and the charging current for thinner oxide is larger. However, (I.sub.p) is limited by the magnitude of the ion current (I.sub.i), and, therefore, the plasma is basically a constant current source for very thin oxides.
Comparison with the MNOS and EEPROM techniques
Wafers containing electrically programmable nonvolatile memories (e.g., metal nitride oxide silicon (MNOS) or electrically erasable-programmable read-only memory (EEPROM) devices) have previously been used to sense the peak surface voltage across a wafer (22,23). This is accomplished by measuring the threshold voltage shift. Such test devices have self-limiting current conduction characteristics. When the memory device is charged up, it takes a large voltage to pass any small current through the dielectric layers. The charge-up voltage determined with EEPROMs is, therefore, different from and much larger than that appearing on a thin-oxide MOS. Also, EEPROM programming ((V.sub.T) shift) is completed within 1 msec. An EEPROM device will record voltage transients lasting milliseconds, even though such short transients cause little charge passage through the oxide and little damage compared with a stress lasting many seconds (26).
Can plasma damage be cured by annealing?
Doubts have been raised about whether interface traps ((N.sub.it)) produced by plasma etching are a genuine indicator of device damage or merely a monitor of process stress. If such traps are eliminated in the annealing that usually follows metal etching, then perhaps they have no practical significance.
To pursue this issue, the density and energy distribution of interface traps caused by plasma etching can be extracted from the quasistatic CV curves. When these etched devices are annealed in forming gas at 400 (degrees) C for 30 minutes, interface traps are completely passivated, presumably through the formation of Si-H bonds. Electrical stress is then applied to the annealed devices and virgin wet-etched controls. The excess (D. sub.it) in the annealed plasma-treated case is quite evident, as is the similarity in the shapes of curves A and C. In the annealed plasma-etched devices, interface traps created during Fowler-Nordheim stressing are generated in proportion to initial charging during the etch, i.e., those near the wafer center revert to a higher (D.sub.it). Even though the interface states are passivated during forming gas annealing (B), about 60% of the traps reappear after subsequent stressing (curve C). Since the bonds formed between hydrogen and silicon during annealing are very weak (0.3 eV), they are probably easily broken when electrically stressed. The conclusion is that the damage caused by oxide charging is latent and remains, even after annealing.
Oxide yield and long-term time-dependent dielectric breakdown
Figure 11 compares the predicted distribution of charge-to-breakdown ((Q. sub.BD)) for 1-(mm.sup.2) oxides after plasma ashing (solid lines) for two antenna pad ratios with the (Q.sub.BD) distribution of corresponding wet-processed oxides. The predicted curves agree well with the data. The yield for these antenna ratios after ashing was only about 70% or 20% for antenna ratios of 1 or 9, respectively. Figure 12 shows the (t.sub.BD) distribution of oxides that have survived etching and ashing, respectively. Since the effect of plasma stressing is, in a sense, similar to oxide burn-in, the weak oxides break down during the plasma process. Therefore, the surviving oxides generally have longer lifetimes than the control oxides.
Summary
Plasma processing creates interface traps that can be used to deduce an equivalent average stress current or voltage experienced during processing. Plasma-induced oxide- charging current can be determined by comparing CV shifts from the process to those for stressed control devices. Charging current, collected only through conductor (antenna) surfaces exposed to the plasma during etching, is proportional to a) conductor peripheral length for Al and polysilicon (photoresist-on case) etching and b) to pad area during resist stripping and photoresist-off cases. The plasma acts more like a current source than a voltage source, which has favorable consequences for the thin oxides of future devices. Although interface traps can be passivated with a forming gas anneal, the passivated devices are more vulnerable to damage during subsequent Fowler-Nordheim stressing. Plasma processing lowers oxide yield, but oxides surviving processing have longer lifetimes than unprocessed controls.
Acknowledgment
The authors thank Dr. D. L. Flamm for his critical review of the manuscript and helpful suggestions. Part of this research at UC Berkeley is sponsored by SRC, Sandia Laboratory, Signetics, TI, Rockwell International, and AMD under MICRO program and ISTO/SDIO administered by ONR under Contract N00014-92-J-1757.
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HYUNGCHEOL SHIN received B.S. and M.S. degrees in Electronics Engineering from Seoul National University in 1985 and 1987, respectively. He is currently working toward a Ph.D. degree in Electrical Engineering at the University of California, Berkeley. Shin has been an intern at Applied Materials in Santa Clara, CA, since 1992. He has authored and co-authored 19 research papers.
NEETA JHA received a B.Sc. degree in Physics from Leeds University, England, and a M.Sc. in Solid State Electronics and Ph.D. in Electrical Engineering and Electronics from UMIST, University of Manchester. Jha joined Applied Materials in 1988 and is a senior process development engineer, working on plasma process induced device degradation.
XUE-YU QIAN graduated from the department of Physics at Beijing University, China, and received a Ph.D. degree in Physics from the University of Michigan in 1987. Before joining Applied Materials in 1990, Qian held various positions at the University of Science and Technology of China and the University of California at Santa Barbara and Berkeley.
GRAHAM W. HILLS is director of Technology at Applied Materials. He received a B.A. degree in Natural Sciences and a Ph.D. in Physical Chemistry from Cambridge University, England. Prior to joining Applied Materials in 1989, he was a member of the technical staff at AT &T-Bell Laboratories. Hills has published approximately 50 papers on plasma etch, device integration, and various spectroscopic techniques.
CHENMING HU received a B.S. in Electrical Engineering from the National Taiwan University and M.S. and Ph.D. degrees in Electrical Engineering from the University of California, Berkeley. From 1973 to 1976 he was an assistant professor at MIT. He joined the University of California, Berkeley, as a professor of Electrical Engineering and Computer Sciences in 1976. Dr. Hu has authored or co-authored three books and more than 300 research papers. |
