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To: Paul Engel who wrote (50755)	3/18/1998 10:30:00 PM
From: Yousef	Read Replies (1) \| Respond to of 186894

Paul, Re: "IBM's paper at the ISSCC described their copper technology and performance using a PowerPC chip." Today, I got a copy of the IBM ISSCC paper and a copy of the slides presented (from the slide supplement to the proceedings). Re: "Their measurements indicated a 40% reduction in RC delays, ALL OF WHICH WAS ATTRIBUTABLE TO REDUCED CAPACITANCE!" However, IBM's slides indicate that Copper Rs is about 40% lower than equivalent (thickness/width) aluminum. I believe looking at the difference in backend design rules between the two processes, IBM has reduced the copper interconnect linewidth to maintain equal resistivity compared to aluminum while IBM has widen the space between lines thus lowering the capacitance laterally (between lines) and vertically (due to narrower width). This is how IBM achieves the lower capacitance while having the same resistance. Re: "IBM 2.5V versus 1.8V process" IBM compared two processes ... one that had aluminum interconnect and 2.5V devices to a copper interconnect with 1.8V devices. Also, the 1.8V devices had an Leff of .12um (printed gate at .20um) ... these are comparable to the most advanced Intel .25um process. IBM's measured speed of the PowerPC improved by 27% due to moving from 2.5V to 1.8V devices while the copper interconnect accounted for a 12% improvement in speed. Thus the incorporation of copper interconnect (even at .25um) can produce "decent" improvements in CPU speed. Copper interconnect is the direction that everyone will head in the near future and companies will also incorporate Low K dielectrics as they make this move. This change in the interconnect will account for significant speed improvements. Yousef