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Technology Stocks : Atmel - the trend is about to change -- Ignore unavailable to you. Want to Upgrade?

To: Doug Skrypek who wrote (8039)	3/18/1998 6:20:00 PM
From: eDollar.com	Read Replies (1) \| Respond to of 13565

We have to closely watch what ATML says in its earnings release. Any one buying at any lever is not a good idea, knowing such a downdraft in the stock. I think it is highly possible that all the FABS that were producing DRAMS are now migrating to producing FLASH. If there is price erosion, FLASH memory will suffer the same fate at DRAM and SRAM makers (MU, IDTI, CY etc). This stock will triple or quadruple for sure, but I dont know from which price. may be 14 or 8 or 4 ?

To: Doug Skrypek who wrote (8039)	3/18/1998 11:05:00 PM
From: Mang Cheng	Respond to of 13565

"Joins European electronics consortium -- Cadence targets RF design" By Peter Clarke March 16, 1998, TechWeb News Munich, Germany - Cadence Design Systems GmbH, the German subsidiary of Cadence Design Systems Inc., has joined a consortium of European electronics companies attempting to improve design methods for wireless system architectures and RF circuit design. The consortium is working within the RF Front End project, a three-year program that aims to refine design methods to improve and speed up RF circuit design, and at the same time help integrate it within the wireless-systems design flow. The German government is providing 50 percent of the project's $9.2 million funding. The project will work on RF circuits for the forthcoming Universal Mobile Telecommunication System (UMTS) communications standard and for applications in the unlicensed instrumentation, scientific and medical (ISM) band. UMTS, intended as one of the communications standards for next-generation mobile terminals, will work at frequencies around 2 GHz. It is due for deployment in 2001 or 2002, shortly after the RF Front End project is set to conclude. Project participants include mobile-communications equipment maker Nokia; the Temic IC division (Heilbronn, Germany), which was recently sold to Atmel; and Thesys Microelectronics GmbH (Erfurt, Germany), along with a number of German universities and technical institutes. "We want to get the CAD environment so that we can start from a system specification and move down to RF circuits in a consistent way," said Gerhard Schaefer, CAD manager at Temic. "Such things are known in the digital domain and we want to achieve that for high-frequency circuits. It's not [about] developing new tools but improving Cadence's Spectre [RF circuit] simulator and developing new methods." Temic will apply the methods developed to the design of RF circuits in its silicon-germanium process technology, Schaefer said. Thesys hopes the project "will improve modeling of complex RF blocks," said Peter Gregorious, BiCMOS IC design manager at Thesys. "At the moment they are more or less handcrafted at the transistor level. At higher levels, where we need to be, behavioral modeling is not efficient, nor is it accurate enough." Simulation technology Gregorious said his company would be looking at producing BiCMOS circuits to work in the ISM band for such applications as keyless door entry. A major component of the project's methodology will be the development of Cadence simulation technology. As part of its contribution, Cadence has assigned five engineers from its Munich office to the project. It will also supply its Alta SPW, Analog Artist design system and Spectre RF circuit simulator. Tony Stone, analog and mixed-signal marketing manager at Cadence, said there was nothing wrong with tools like Spice and Spectre. "But there is more to wireless design than can be assessed via one tool," he said. "Cadence is addressing this issue across all technology fronts and is moving toward highly productive design flows" rather than point tools. In most wireless projects, RF circuits are designed separately, and on different time schedules, than other parts of the system. This makes it difficult to perform system-wide trade-off analysis and partitioning, and introduces the possibility that the RF and baseband electronics may not work correctly together after all the chips are fabricated. At the same time, design time scales and product life cycles for cellular handsets and terminals are getting shorter. "There have been numerous advances in top-down wireless design flows for logic and DSP design, but until now, the RF section has been out on its own little island," said Bill Portelli, vice president and general manager of Cadence's custom IC business unit. "The lack of strong system-through-RF design flows is turning into a bottleneck, especially as people try to put entire phones on one chip." Stone would not predict whether particular EDA tools would result from the program. "The rationale of joining a consortium is to work together to develop a consistent flow and methodology and learn from the process." techweb.com Mang