"Altera, Xilinx split on next PLD wave"
(Mang note : what does the highlighted paragraph about atmel means ?)
By Ron Wilson March 02, 1998, TechWeb News
Monterey, Calif. - The two leaders of the programmable-logic
industry-Altera Corp. and Xilinx Inc.-are taking starkly different approaches
toward what may be the fastest-growing area in the high-density PLD
market. The strategies, spotlighted here last week at the Association for
Computing Machinery's FPGA'98 conference, are gambles for both parties
and could either cement or overturn Altera's regained market-share
dominance.
The emerging market at issue is that for reconfigurable computing
devices-field-programmable gate arrays or complex PLDs that can be
reconfigured task-by-task. Reconfigurable computing allows two benefits: A
single device can be used to implement many times its physical capacity in
circuitry, and large, slow, complex general-purpose circuits can be replaced
with small, fast data-specific ones.
The upshot can be a dramatic increase in performance. A poster-session
paper presented here by Takashi Miyamori and Kunle Olukotun of Stanford
University described a reconfigurable media signal coprocessor, implemented
in an FPGA, that can outperform conventional techniques by two to more
than 20 times on DES-encryption, MPEG-2-decoding and
MPEG-2-encoding tasks.
Mainstream PLD companies have viewed reconfigurable computing as either
a sleeping giant or a red herring. Some believe the techniques could account
for much of the programmable-logic industry's growth in the coming years.
Others think the idea, limited by the complexity of partitioning and the lack of
tool support, will never spread beyond research papers and a few
signal-processing applications.
The sleeping-giant view was advanced at the conference by two engineers,
neither of whom could be identified on the record, who told of substantial
growth and major contracts happening this year. "It's nearly invisible," one of
the engineers said, "because our customers are so concerned with secrecy.
They see these techniques as such a superior approach to their application
that they are trying to keep the competition off the track as long as possible."
The other designer described a recent contract in which the customer insisted
that the FPGA package in his reconfigurable system be re-marked as a gate
array to avoid raising the suspicions of his competitors. "They don't want
people to know what they are doing, partially because right now there's no
way for them to protect their code," the designer said.
If reconfigurable computing represents a blossoming opportunity for
reconfigurable FPGAs, it also demands much of the devices. An ideal chip
for the application would be incrementally reconfigurable at high speed while
the rest of the device remained in operation. It would provide a wide bus for
moving configuration data into the chip, or possibly a big on-chip cache for
configurations. And it would provide both compression and encryption
facilities, so configuration files could be moved into the parts quickly and in
secrecy.
Among commercial devices, only parts from Atmel Corp. approach that
ideal today. The Atmel devices permit incremental, on-the-fly
reconfiguration.
But both Altera and Xilinx are betting on the market-in different directions.
At architectural odds
Both Altera and Xilinx have investigated reconfigurable computing, and both
companies' devices are used in reconfigurable applications, but there appears
to be a distinct difference in the eagerness with which the two companies
approach the market.
Altera's approach has been to make no commitment to features specifically
for reconfigurability. "Architecture should serve the average user-that is, no
particular user," Altera's Clive McCarthy said in a panel session here. "In this
market, you have to architect for revenue, not for technical needs.
"Wacky features that are only going to be used by a minority of customers
are going to be paid for by everyone else. Worse, they are going to burden
your software developers and take your focus off of doing the best job for
the average user."
Sandeep Vij, vice president of marketing at Xilinx, presented an entirely
different perspective. "You stay the leader by thinking a generation ahead of
your customers' present needs," Vij said.
Whereas Altera focuses on streamlining its die size on mainstream devices,
Xilinx has quietly begun to swing all of its FPGA product lines into sync with
the needs of the reconfigurable movement.
The first indication of Xilinx's intentions came during a conference last year,
when a researcher described an experimental XC4000E device that had eight
planes of configuration memory, with each flip-flop in the chip backed by
eight state registers. Those facilities allowed the device to change its
configuration in a matter of a few clock cycles, storing the state of the
flip-flops and passing it to subsequent configurations.
Such a part is not likely to show up on stockroom shelves soon. Xilinx
researcher Steve Trimberger said the chip was nearly three times the die area
of a conventional XC4000E, and noticeably slower; power consumption in
operation could range in the double digits. But Trimberger demonstrated
techniques for systematically partitioning extremely large circuits, loading them
into the eight configuration memory planes and executing very demanding
applications from a single chip.
More recently, the Xilinx XC 6200 device was announced with significantly
improved facilities for on-the-fly reconfiguration.
A source close to Xilinx said president and chief executive officer Wim
Rolents has decided that every new Xilinx FPGA family will have such
facilities in the near future. "He believes in this market," the source said.
The contrast between the Altera and Xilinx approaches will play out in the
market in the next year or two. If, in fact, the reconfigurable market grows
slowly and remains a tiny minority of designs, Altera may gain advantages in
cost and simplicity.
techweb.com
Mang |
