SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?


To: gnuman who wrote (50805)3/19/1998 12:23:00 PM
From: Tony Viola  Read Replies (2) | Respond to of 186894
 
Gene, about Albert Yu saying Celeron chips won't have an L2 cache, I think he was misquoted, as you allude to. Either that, or he was referring to the first Celeron, code-named Covington. The Intel page I URL'd in the post yours is in response to said that the second Celeron, code-named Mendocino, would have up to 256K of L2 available.

BTW, FWIW, I have talked to our system performance architects about the importance of L2 cache, and, they said, as I suspected, for Windows 98 type applications, such as Word, Excel, Project, etc., it won't be missed at all. Sure, you won't use Covington in a server or high speed workstation. That's not what it is targeted for. It's kind of like you wouldn't put a 120 horsepower engine into a Corvette, but, in a Honda Civic, it will do just fine.



Tony