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Technology Stocks : Osicom(FIBR) -- Ignore unavailable to you. Want to Upgrade?

To: David Wise who wrote (6014)	3/19/1998 4:47:00 PM
From: David Pawlak	Respond to of 10479

Yes, there will be additional products added on not only to the NET+ARM technology, but the IQX and the GigaMux as well. They are all in the works right now and are currently slated to be introduced within the next 3 - 12 months from what I understand.

To: David Wise who wrote (6014)	3/19/1998 10:17:00 PM
From: Jim Stone_	Read Replies (1) \| Respond to of 10479

5 additional NET+ARM chips planned and a massive integration chip expected to be possible by end of 99. The following was cut and pasted from PDF downloaded from Osicom web site. You can find this along with a nice chart in section 2 the hardware description. Maybe more info than you wanted. NETA 12-0 NOW This is Osicom's current and first offering based upon the ARM 7 RISC processor with a 10/100 Ethernet MAC and all the supporting logic and networking software to make it an ideal solution for connecting to the Internet via Ethernet. It comes with ISI's pSOS embedded kernel and Osicom's full set of networking protocols and applications - all accessible with APIs. The performance of 12 MIPS using commercial flash ROMs is more than sufficient for most data collection, security,building control, computer peripheral server, thin server, etc. applications. NETA 15-0 Planned 3Q-98 This chip is manufactured on the .35 micron process, which will increase the performance to 15 MIPS; in addition, we will add the 10/100 Ethernet physical interface (PHY) to the chip, saving additional component cost. The chip will also support a CAM interface for networking applications and 1451.2 serial interface for industrial sensor support. Massive Integration NETA 40-0 Planned 3Q-98 This chip will be pin and function compatible with the NETA 15-0, but the addition of cache memory will increase performance to 40 MIPS+ for higher end applications as well as provide a smooth growth path for customers. NETA 40-1 Planned 1Q-99 This version of the NET+ARM will add a PCI interface to reduce the cost of overall systems that attach via PCI buses. This chip will either use an ARM 7 with a cache or the ARM 9, depending upon availability. The low cost and high performance of this chip will make it an ideal solution for an intelligent front end for a PC or other products which have a PCI bus structure. NETA 120-0 Planned 2Q-99 This chip will be the highest performance model and will be compatible with and supersede NETA 40-0. It will be based on the ARM 9 processor, giving it 120 MIPS performance. The goal is for it to have the same selling price as the NETA 40-0. NETA 15-L Planned 2Q-99 The NETA 15-L will be the lowest cost member of the NET+ARM line. Its goal is to bring the cost of connectivity even lower. It will use the most advanced manufacturing technology available at the time combined with a cost-reduced logic design. Our goal is a price of $10. NETA MI Projected 4Q-99 ASIC technology is constantly evolving; chips are becoming more dense, new cells are becoming available and development tools are improving. Applications which would be cost-prohibitive today will not be tomorrow. While putting Flash ROM and RAM on chip today doesn't appear economical, it is very likely that it will be by the end of 1999. It is the intention of the NETA MI to integrate as much as is economically feasible at the time.