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To: Yousef who wrote (5128)	3/20/1998 4:23:00 PM
From: FJB	Read Replies (2) \| Respond to of 6843

Yousef, RE:"Intel will present a paper at the VLSI symposium (early June) where they will describe reduced gate linewidth for their .25um process. This will now give them about 15% - 20% improvement in CPU speed due to increased FET (P & N) drive currents." In simplest terms(for the layperson), what is the relationship between linewidth and FET drive currents? Also, what's the formula for this relationship? TIA, Bob

To: Yousef who wrote (5128)	3/20/1998 9:34:00 PM
From: Paul Engel	Read Replies (1) \| Respond to of 6843

Yousef - Re: ""Intel will present a paper at the VLSI symposium (early June) where they will describe reduced gate linewidth for their .25um process. This will now give them about 15% - 20% improvement in CPU speed due to increased..." Under pressure from competitors, the DOJ has mandated that Intel NOT publish this paper and NOT implement those process "tweaks". The DOJ has warned Intel that its superiority in wafer fab process development and deployment has put them (Intel) into a monopolistic position. The People's Republic of AMD and Cyrix have protested and the DOJ wants to "level the playing field". Paul