Sounds like competition, and on the same day
Samsung Launches Global High Performance ASIC Thrust; Adds Embedded SuperSRAM, Flash, Mixed-Signal Cores
SAN JOSE, Calif.--(BUSINESS WIRE)--March 23, 1998--Samsung Semiconductor today announced worldwide availability of a full suite of high-performance ASIC design services, embedded memory, intellectual property and mixed-signal process technology optimized for System-On-a-Chip (SOC) integration.
With the addition of embedded SuperSRAM and Flash, as well as mixed-signal building blocks such as PLLs, CODECs, ADCs and DACs, Samsung's Intelligence-On-Silicon initiative is moving aggressively to address the core-based SOC market, an opportunity that is expected to grow at a compound annual rate of over 40% between 1996 and 2001, according to Farzad Zarrinfar, associate director of ASIC marketing at Samsung in San Jose. Samsung expects to see its ASIC revenues triple over the next year.
The new products and services offered by Samsung through Intelligence-On-Silicon are specifically directed at communications, portable computing and consumer SOC applications. These and other high-performance SOC applications require the strengths of Samsung*s Intelligence-On-Silicon: lower cost, maximized bandwidth and minimum power dissipation. Samsung now offers the most complete set of Embedded Memory-based high performance SOC solutions available and will drive the growth of SOC design among its customers worldwide.
"Our customers need access to the full range of high performance process technology, memory and mixed signal cores in order to move to a System-On-a-Chip design methodology," Noel Park, Vice President/General Manager, System LSI Group, said. "The depth and breadth of our Intelligence-On-Silicon design support and manufacturing process technology allow our customers to take full advantage of the cost and performance benefits of SOC designs."
Samsung's ASIC Technology
Samsung's ASIC process is driven by fabrication of the 21164 Alpha microprocessor which can clock up to 600 MHz. Digital ASIC technology is complemented by the addition of new mixed-signal technology that allows the integration of pure analog or analog/digital functions on a single chip. This technology supports an operational voltage of 2.5V to 3.3V, with 3.3V/5V standard and optional dual oxide enhancement for true 5V I/Os.
The new embedded SuperSRAM and Flash capability is an extension of Samsung's Merged DRAM and Logic (MDL) efforts and provides a high performance memory alternative to package memory components. SuperSRAM and Flash are optimized to provide significant performance, cost saving, and reliability benefits for SOC design.
Embedded Flash
The embedded Flash memory is used for code storage and data retention for applications such as cellular phones, pagers, telecom systems, answering machines, network equipment, PC peripherals, GPS, HDD, ADSL modem, digital camera, reconfigurable systems and set-top boxes. The embedded Flash technology is based on Samsung's standard CMOS supplemented with six additional mask steps which is implemented using field enhancing tunneling injector split-gate architecture.
This architecture is optimized for security, high speed and high data retention. This flash technology achieves its high reliability with a much thicker oxide layer than that which is used by most flash architectures. This technology has resolved 'erase disturb,' because all bytes are simultaneously in the same page and each page is completely isolated from every other page during any erase operation. This NOR-based Flash cell employs poly-to-poly Fowler-Nordheim tunneling for erasing and source side Channel Hot Electron injector for writing. An on-chip charge pump generates internal high voltage on the word line during erase on the source line during writing. Flash has a read access time of below 150 nanoseconds at 3.3V with endurance of over 100,000 cycles guaranteed and 1 million cycles typical with 20-year data retention at 125 degrees C.
"Because of the added functionality in system reprogrammability afforded by embedded Flash, it will continue to be an important enabler of SOC applications," said Alan Niebel, analyst with Semico Research, Phoenix, AZ, who recently completed a study of the embedded Flash market which shows tremendous growth potential for this type of application.
Embedded SuperSRAM
The embedded SuperSRAM technology used by Samsung is a synchronous SRAM with 4-transistor cell architecture optimized for small die size and power reduction, while it maximizes performance in SOC designs such as Ethernet Switches, where lower power, lower cost, and optimized performance is critical.
SuperSRAM is used for cache or packet-buffer memory in network switches, routers, cellular base stations, and multi-processing servers. Embedded SRAM, for 1-4Mbits, beats discrete parts in the critical memory metrics of bandwidth, granularity, transmission line effects, and power consumption.
Discrete SRAMs with 4-byte-wide data buses run at speeds of 200MHz with a maximum theoretical bandwidth of 800 Mbytes/second. At 100MHz, embedded SRAMs with 32-byte-wide (256 bit) data buses, will reach a bandwidth of 3.2 Gbytes/second.
The finer granularity of embedded SRAM translates to less money/area/power wasted for unused memory cells when the SRAM blocks are configured to an exact number of bits and word. Power consumption is one fourth that of discrete SRAMs because at least one set of input and output pins must be driven for a packaged SRAM to communicate with a logic chip, but an embedded memory only has to drive the wires on the chips itself.
The average size of the embedded SRAM cells has been reduced to 10.2 micron 2 by using two lightly dropped poly resistors placed on top of four transistors to keep the SRAM cell small. Cost of the die is reduced because it is based on a standard CMOS process with five additional mask steps. Also, Samsung uses a self-aligned contact process that closes the spaces between transistors. SuperSRAM is supported by BIST (Built-In-Self-Test) which is provided by Samsung as a soft core, along with IDDQ and scan-ATPG test methodology. SuperSRAM's memory BIST technology reduces time to market by eliminating test vector generation at the system level. |
