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To: nigel bates who wrote (949)	3/29/1998 4:52:00 AM
From: Artslaw	Respond to of 1305

I can tell you one thing: Cornell's statement about their etching (111) silicon not being directly relevant to the semiconductor industry is an understatement. Logic chips are built on (100) substrates, which have the lowest number of atomic bonds along the exposed surface plane (where the active devices will be fabricated). (111)-oriented wafers have the highest number of bonds. At the surface, these bonds have nothing to attach themselves to, so are "dangling." Dangling bonds degrade performance, which is precisely why (100) orientation is used. Finding a way to make 'flat' (100) is great, but I can't even think of an application for flat (111) except to study interface properties. (Well, actually, a lot of MEMS are designed on non-(100) surfaces). The (###) are Miller indices, and refer to the orientation of the silicon crystals. Etching is very orientation-specific, so whatever is developed for (111) will work quite differently on (100). How does it affect IPEC? Not at all, IMHO, unless they don't understand the difference. :) Steve

To: nigel bates who wrote (949)	3/30/1998 10:52:00 AM
From: Andrew Vance	Read Replies (2) \| Respond to of 1305

I read the article and it was very impressive. However we may be talking about apples and doughnuts here. The type of smoothing talked about is on the atomic level which will affect the quality of the surface and/or interface performance of devices created. The IPEC version of CMP would be used first to smooth out the major(gross) 3-D topography on the 1000s of angstrom level. I hate to use cooking as the example but IPEC CMP goes out and takes a lopside cake and makes it dimensional perfect such that an even layer of frosting can be spread over it. The smoothing in this article you posted attempts to smooth out the airy bubbles on the surface of the cake. Andrew