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To: Tony Viola who wrote (51676)3/31/1998 2:35:00 PM
From: Paul Engel  Read Replies (1) | Respond to of 186894
 
Tony - Re: "Are you sure that the L2 cache for Mendocino will be on the same die as the processor? the reason I wasn't sure is that a PII, and 256K of L2 sounds like too much for one die. Anyone else?"

The Mendocino WILL HAVE an L2 SRAM cache grafted on to the same silicon as the CPU itself.

However, I think the first version will have 128K of L2 cache - not 256K.

The die size increase will be big (an additional 6.29 million transistors!)- IF Intel uses the same 0.25 micron process.

I am speculating that the Mendocino may be designed/fabricated on the new 0.18 micron process - to keep the die size down, and hence costs, as well as increasing performance.

This would also provide a "roto rooter" vehicle for ramping up the 0.18 micron process in preparation for Merced.

Paul