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To: Elmer who wrote (51760)	3/31/1998 11:07:00 PM
From: Paul Engel	Respond to of 186894

Elmer - Re: " Shouldn't this have a further effect on reducing the die area of the added L2 cache, beyond the .18u shrink?" Local interconnect can greatly reduce the size of SRAM cells which have a lot of metal strapping to form cross-coupled latches connecting the 2 P-channel and 2-n channel transistors into a "latch" configuration. Saving a square micron or two on this cell gets MULTIPLED by 8 (8 SRAM Cells/BYTE) and Multiplied Again by 2^15 (32 K) or 2^16 (64 K) or 2^17 (128 K), depending upon the size of the cache. The Mendocino will have BOTH a 32 KiloByte L1 Cache and a 128 KiloByte L2 cache. Any small area saving due to local interconnect adds up - QUICKLY! Paul