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Technology Stocks : CYRIX / NSM -- Ignore unavailable to you. Want to Upgrade?

To: Joe NYC who wrote (25794)	4/8/1998 10:57:00 PM
From: FJB	Read Replies (2) \| Respond to of 33344

Joe, I've read a quite a few articles over the past couple days and didn't bookmark them all, so I don't where to find the one where I read this. But the predicted x86 performance of Merced at intro will be about equal to that of a 500MHz PII. Bob

To: Joe NYC who wrote (25794)	4/8/1998 10:58:00 PM
From: Steve Porter	Read Replies (1) \| Respond to of 33344

Joe, The ideal thing would be to have a CPU that does a lot every cycle AND high clock speed. Merced will apparently have both. Nope.. sorry.. but the ram speeds that are currently available won't allow that.. it's that simple.. even with RBusDram the big penalty comes for the first byte clock hit.. with the BEST Sdram interface it is 3 bus cycles.. if I go to ram for an add (integer) I have the following happen: 3xclock multiplier fetch ram (on pentium 233 that equals ~10.5 cycles) 1 clock do the math.. If Intel really wanted to make money, they should get into 1 ns DRAM.. they wouldn't even need to make CPUs anymore.. everyone and their uncle would need 1ns DRAm (or want it anyway) and Intel could patent the process.. With 1ns Dram and a 200Mhz bus speed, a 200mhz P55C with ZERO L2 cache (wouldn't need it) would out perform anything current available.. (and a Cyrix chip under the same circumstances would be even faster). Steve Cyrix/NSM Rule!