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To: Curlton Latts who wrote (16449)	4/9/1998 10:50:00 PM
From: BillyG	Respond to of 25960

Hitachi .2 micron chips.................. techweb.cmp.com Posted: 9:00 p.m. EST, 4/9/98 Hitachi prepares 0.20-micron process for production By David Lammers TOKYO - Hitachi Ltd. will start volume production this fall of cell-based ICs using a 0.20-micron (drawn) process technology. While IBM Microelectronics, LSI Logic Corp. and others have announced 0.20- to 0.18-micron products, Hitachi is the first Japanese vendor to do so. NEC Corp. expects to make an announcement this spring. Hitachi announced a 0.25-micron (drawn) cell-based product series last February. Limited volume production begins in June. "We will make 0.25-micron CBICs for some customers [at that process point]," a spokesman said. "But most . . . will go from 0.35 to 0.18 micron." What Hitachi calls its 0.35-micron generation uses 0.4-micron (drawn) design rules with a channel length (Leff) of 0.35. At 0.25 micron, both the drawn and Leff measurements are 0.25. The 0.20 generation has an Leff of 0.18. After that, Hitachi may jump to 0.15 or 0.13 by 1999 or early 2000, depending on tool availability. At 0.20 micron, the "HG75C" series offers power-consumption advantages, 400-MHz peak operation and a gate-delay time of 75 ps. With a 1.8-V power supply, typical of battery-driven systems, power dissipation is rated at 0.04 microwatt/gate/MHz, compared with 0.07 microwatt/gate/MHz at 0.25 micron and 0.26 at 0.4 micron. Power consumption is one-fifth that of the 0.35-micron generation, the spokesman said. By late '98, a faster SH-3 RISC core will be ready, with DRAM and flash modules to follow. The cell library is compatible with VLSI Technology Inc.'s, though each company uses its own process technology, a spokesman said. The companies offer cores optimized for logic synthesis. Hitachi will start taking orders in June, with volume production set for October. Quad flat packs will be standard at first but Hitachi is developing 112- to 264-pin chip-scale packaging.