Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Jim McMannis who wrote (31682)	4/10/1998 1:06:00 PM
From: Paul Engel	Respond to of 1571445

Jim - Re: "Other boxmakers might try one but Compaq, ACER and IBM will likely push the K6 in that price range." They already do. I think that is the point. Paul

To: Jim McMannis who wrote (31682)	4/10/1998 3:47:00 PM
From: Ali Chen	Read Replies (2) \| Respond to of 1571445

Why Celery is cacheless? - Cost of cache. Current P-II 233-300 use 4 pieces of 167MHz CMOS 1Mbit Synchronous SRAM [æPD431632L] As per NEC (old) news release ic.nec.co.jp "price of the new product is expected to be 2,000.=$15" So, 4x15=$60 alone, maybe $40 today. At least. Count on other parts of P-II brick: 1 IC: i82459 - probably TAG RAM and/or ECC; 1 Printed board, 12 layers at least; 92 SMT capacitors; 12 SMT resistors; 36 SMT resistor networks; 1 Aluminium thermal plate 130x50x4mm, precisely machined in all six surfaces, plus some fine grooves; 2 spring holders, steel; 8 machined pins, steel; 4 parts of plastic cover with locks; ----- So, Q: How much it may cost to assemble all this? To order and supply parts? For quality control? For "Deschutes"(?) P-II-333 and up, somewhat faster synchronous cache must be used. If it would be again from NEC, then it could be æPD464318L/36L or æPD464518L/36L or alike. Again, in accord with ic.nec.co.jp "The price of the new products is 20,000 yen to 25,000 yen per unit," or $150+. Not too shabby. No wonder Intel is going to manufacture this cache themselves, 222mm2 die size on 0.35um technology (as Pauleron told us). In any way, silicon area is silicon area, no matter what you print over it. 130 + 222 seems to be smaller than 68mm2 for Intel stalwarts. Sounds interesting. BTW, Celery today: 3 vendors, 199-212 price range.