NEC Unveils Advanced ASIC Processes
(04/24/98; 1:42 p.m. ET)
By Crista Souza, Electronic Buyers' News
In what may amount to a title defense of its ranking as the industry's leading Application Specific Integrated Circuit (ASIC) producer, NEC Electronics on Monday will unveil its 0.18-micron and 0.15-micron chip processes for consumer electronics and high-end graphics designs.
The processes, which are slated to begin production in the fourth quarter, are based on a seven-layer grid that packs 80,000 usable gates/square millimeters to produce low-power chips operating at up to 500 megahertz.
Santa Clara, Calif.-based NEC (company profile) joins the growing ranks of chip suppliers that have marched out similar technologies targeting the same customer base. The competition is mounting, but NEC seems to be holding its own.
"I think we will still be number one in 1998, 1999, and 2000, but we have to watch Lucent and IBM very closely," said Hirokazu Hashimoto, vice president of semiconductors at NEC.
Although NEC has led in ASIC revenue for the past five years, Lucent Microelectronics, Allentown, Pa., and IBM Microelectronics, Fishkill, N.Y., have made significant market-share gains and now hold the No. 2 and No. 3 spots, respectively.
How well suppliers are able to fill out their ASIC libraries and execute designs will determine the shape of the competitive landscape over the next few years, said Bryan Lewis, an ASIC analyst at Dataquest, San Jose.
"There is a lot of specsmanship in the ASIC world, but it looks like NEC's process road map is more aggressive [than others] in terms of density per square millimeter," Lewis said. "More gates means they will have a good cost structure, and that's important to customers."
However, the ASIC pecking order is threatened by more than just technology advancements. Commodity suppliers, such as Samsung Semiconductor, are looking to enter the emerging system-on-a-chip ASIC market and are blurring the lines, said Jerry Karls, president of Integrated Circuit Engineering, a Scottsdale, Ariz., market research firm.
At the same time, pure-play foundries are migrating to the ASIC design realm through alliances with third-party vendors of intellectual property libraries.
"It's no longer a question of who's got the technology," Karls said. "It's how many people are going to start playing in what we call the ASIC market."
In October, NEC's customers will be able to start designs with the 0.18-micron (drawn) unified CMOS (UC3) process, which is designed to support low-power mainstream consumer technologies. In the fourth quarter of 1999, NEC will offer its 0.15-micron (drawn) unified RISC (UR3) process, which is targeted at high-end graphics and networking customers.
Libraries supporting the processes are expected to be available in October, including three new MIPS processor variants operating from 133 MHz to 200 MHz, modular embedded dynamic RAM up to 32 megabits, a Direct Rambus ASIC cell, and IEEE 1394 support. In addition, existing 0.25-micron cores will be ported to the new processes.
Initially, NEC will use copper interconnects between transistors, with aluminum interconnects between metal layers to avoid performance degradation at tighter device geometries. The 0.15-micron UR3 process will feature an all-copper wiring scheme.
A typical design using five metal layers, standard cores, and 696-pin BGA packaging is about $410 per unit in 10,000s, NEC said.
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