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Technology Stocks : The New QLogic (ANCR) -- Ignore unavailable to you. Want to Upgrade?

To: Alan Aronoff who wrote (16032)	4/30/1998 2:41:00 PM
From: Patrick Sharkey	Read Replies (1) \| Respond to of 29386

Ancor also has stated that Lockheed Martin is a customer, although it is not clear that Ancor is working with LM on any defense department projects.

To: Alan Aronoff who wrote (16032)	4/30/1998 11:50:00 PM
From: George Dawson	Respond to of 29386

Defense stuff from 1997 - note in the references Myrinet, SCI and FC may be competitors for this technology. The target cost/unit is $2K for what sounds like adapters-no switch info. "N98-038 TITLE: Low-latency, Protocol Independent, Network Interfaces for Advanced Avionics Systems OBJECTIVE: Develop high-performance network interfaces consisting of protocol independent (either message passing or shared memory) software, and very low-latency hardware, which enhance portability, and interoperability between networks and computer architectures in advanced avionics computing and communications systems. DESCRIPTION: Next generation avionics systems will require dramatic increases in processing to support capabilities such as digital receivers, battlefield wide information networks, and multi-platform, multi-sensor fusion. These systems will exploit parallel and distributed computing and will require concomitant orders of magnitude increases in network capacity and orders of magnitude decreases in latency. Commercial-off-the-shelf (COTS) technology must be used to control costs. One of the major impediments to the development of COTS-based high-performance computing and communications is the processor-interconnect interface. Current components emphasize heavyweight software interfaces and I/O-bus interfaces which curtail sustainable throughput of gigabit/second interconnects to as little as 100-Mbps and inflate message-passing latency into the milli-second range. This program is targeted at the development of a lightweight software interface for both message passing and shared memory, and a very low latency close-to-the-processor hardware interface. The software interface should provide lightweight communications, low-latency multithreading, application-to-network independence, object request brokering, interoperability, and portability across message- passing and shared-memory networks for distributed and parallel applications. The Common Object Request Broker Architecture (CORBA) development should be tracked and compatibility maintained. The hardware interface should provide throughput approaching either the processor-memory bandwidth or the sustainable interconnect throughput (whichever is less), with latencies of less than one microsecond, at a unit cost of less than $2000 in quantity. In addition, a ruggedized version of the hardware interface should be capable of operating over the military temperature range. PHASE I: Demonstrate feasibility of the interconnect interface by modeling and simulation of software and hardware throughput, latency, cost, functionality, size, power, and weight. Evaluate and select the COTS-based processor architecture, software components, and interconnect, to be supported. PHASE II: Develop and demonstrate software and hardware interface prototypes. Evaluate prototypes for throughput, latency, cost, functionality, size, power, and weight. The results of this evaluation should be used to verify Phase I modeling and simulation results and to estimate the unit cost of military and commercial interface systems. PHASE III: In conjunction with a commercial interconnect vendor, develop a low-cost integrated module and software suite suitable for both commercial and military applications. COMMERCIAL POTENTIAL: The high latency and low throughput of software and hardware interfaces for high-performance interconnects currently available represents a major limitation to their introduction into commercial distributed and parallel clusters of workstations. The development of low-latency, high-throughput interface components would represent a breakthrough in the field of high-performance computing and communications. It would revolutionize the effectiveness of the many hundreds of thousands of COTS- based clusters of workstations in the field to better exploit advances in distributed and parallel computing. REFERENCES: 1. IEEE 1394.2 Serial Express (Draft); 2. IEEE 1596-1992 Scaleable Coherent Interface; 3. Myrinet: A Gigabit Per Second LAN; 4. ANSI X3.288-1996 Information Technology - Fibre Channel - Generic Services; 5. Joint Advanced Strike Technology Program, "Avionics Architecture Definition, Version 1.0, Aug 9, 1994"; 6. OMG CORBA 2.0/IIOP Specification. KEY WORDS: Avionics data networks, computer architecture, high-performance computing, parallel computing, high- performance communications"