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To: Jeff Fox who wrote (55029)	5/3/1998 12:15:00 AM
From: Jay	Read Replies (1) \| Respond to of 186894

Jeff Re "Why not just a larger L1?" Don't know the answer to that. Indeed I was wondering about the new Rambus memory - if it is so fast why use L-2 cache at all? Is it a latency problem or what?

To: Jeff Fox who wrote (55029)	5/3/1998 12:48:00 AM
From: Paul Engel	Read Replies (3) \| Respond to of 186894

Jeff - Re: " IF your putting more cache on the same chip then why L2? - Why not just a larger L1" The L1 cache controller is designed to cache 32 K Bytes. This would have to be redesigned and the chip "split apart" to drop in the extra SRAM cells to enlarge the L1 cache. From an implementation strategy, it is simpler to just "bolt" the extra cache on to the end of the CPU chip and run the appropriate address/data lines from the on-chip L2 cache controller (already on the CPU). Paul