SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?


To: Kevin K. Spurway who wrote (32470)5/6/1998 2:14:00 AM
From: Paul Engel  Read Replies (1) | Respond to of 1572209
 
Kevin - Re: " Why not just expand the size of the L1 cache and eliminate the problems with cache checking delays?"

That makes the most sense - IF you start with a new design/architecture.

However, changing the L1 cache controller and tag ram and "ripping" the chip apart to expand the L1 cache is major "surgery".

For the Intel Pentium II, bolting the L2 cache on to the end of the chip with appropriate address and data and control lines, and "tweaking" the L2 cache controller - already part of the Pentium II architecture - is a much simpler process.

For AMD, the L2 cache controller has to be added to the K6 as well as the L2 cache.

Paul