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Technology Stocks : CYRIX / NSM -- Ignore unavailable to you. Want to Upgrade?

To: FJB who wrote (26319)	5/5/1998 10:38:00 PM
From: Investor A	Respond to of 33344

A backside L2 cache between the socket 7 and K6-2 is the trick under Jerry Sander's sleeve? If AMD has such a war plan to debut on 5/28, INTC would fall below 50 in no time. I read a wonderful post by Robato Yao from chips newsgroup as follows: ======================================= From: crobato@kuentos.guam.net (Robato Yao) Newsgroups: comp.sys.ibm.pc.hardware.chips Subject: Re: Different between Intel, Cyrix, and AMD Date: 2 May 1998 07:47:41 GMT Organization: Kuentos Communications Inc. Lines: 94 Message-ID: <6iej2t$3b9@lehi.kuentos.guam.net> References: <6iar41$p7b$1@nnrp1.dejanews.com> <354b1220.6916305@news.tip.nl> Reply-To: crobato@kuentos.guam.net (Robato Yao) NNTP-Posting-Host: tataga-185.kuentos.guam.net X-Newsreader: IBM NewsReader/2 2.0 In <354b1220.6916305@news.tip.nl>, nobody@nowhere.com (Vincent) writes: >>Reality: Intel makes the fastest processor for X86 code period. > >Depends. The Cyrix 6x86MX and MII simply kick the shit out of the PII on >business applications, especially if you look at their clock speeds. Oh yeah, >don't reply with Quake XIV blablabla.... We've been through this crap since its >introduction. Is it in the FAQ by the way ? > >>Fact: They cost more. > >Certainly true. > >>Fact: The fastest processor will never be on socket 7. > >Okay, this is true at the moment. If National Semiconductor, IBM and AMD crank >up the clock speeds considerably, socket 7 will rule again. It still rules to my >opinion. > >There's nothing technically wrong with socket 7 or anything in a PGA package. >One of the world's most powerful CPUs, the MIPS R10000, comes in a PGA package >;-) Slot 1 is just a foul marketing gadget. I think, so does Alpha. > >>Fact: Intel sets the standards. > >Not all of them actually. Sometimes their standards are used to annoy other >manufacturers. MMX is a good example. NexGen's Nx686 (later K6) had a completely >independent MMX unit, making it far superior to the current crippled unified >implementation. Too bad AMD had to redesign it to make it fully compatible to >Intel's. Well if you like to know, Cyrix 686MX has a completely independently designed MMX unit, and they had won their case to call those units MMX. > >>Reality: To not accept this will cause you to always be insecure. > >Personally, I don't see any reason to run mindlessly to the nearest store and >buy a PII. Most people actually do that though... > >Don't get me wrong, I respect it when people buy Intel after carefully looking >at the other options. For some reason the people who shout the loudest at Cyrix, >AMD, etc don't have any experience with them, or they just believe the famous >"horror stories". > >regards, > >Vincent (happy Cyrix user) Here is an interesting question. Can you implement a high speed backside cache using the same physical CPU socket part used for Socket 7? The answer is yes and it is already in the neighborhood. From the motherboards used in---yes---Power Macintoshes G3s---they use a physical socket part identical to those used in Socket 7 pieces. The PowerPC G3 sits on top of it, and sandwiched between the CPU and the socket is a small daughterboard with two cache RAMs on it. The daughterboard extends past the side of the socket, exposing the cache RAMs while the fan sits on top of the G3. Like the PII, the G3 uses backside L2 caches. What more, the cache daughterboard can be removable and upgradable. AMD and Cyrix can get a big clue here if they want to implement a backside cache system for a physical socket 7 part. Ironically, Apple used a CPU SLOT system on their previous families of Macs before they went to a socket system for their current line---just the exact opposite happening to PCs. Rgds, Chris ==========================================