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To: Elmer who wrote (6026)	5/7/1998 11:27:00 AM
From: Ali Chen	Read Replies (1) \| Respond to of 6843

Elmer, <some people make claims up out of thin air and can't back them up.> Some people prefer not to waste their time on obvious things like miserable Celron performance. Other people like you prefer to buy Intel's marketing blurb and hype and spread it out. Bad choice. You owe me 30 minutes of research. BTW, speaking about "PCI-to-PCI" or "host-to-PCI" bridges and AGP. Instead of reading the simplified marketing diagrams, better read specs directly: Quota from INTEL 82443LX (PAC) .pdf documentattion: .... "2. Two sets of configuration registers residing within PAC are partitioned into two "logical" PCI device register sets ("logical" since they reside within a single physical package). The first being dedicated to the Host-to-PCI Bridge function (controls the PCI, DRAM and A.G.P. functions, and other AGPset operating parameters). The second set being dedicated to the standard PCI-to-PCI Bridge function that controls the A.G.P. interface address mapping and PCI-standard configuration parameters of A.G.P. (i.e., A.G.P. is seen as another PCI bus from a configuration point of view). NOTE This configuration scheme is necessary to accommodate the existing and future software configuration model. (The term "virtual" is used to designate that no real physical embodiment of the PCI-to-PCI Bridge functionality exists within PAC, but that PAC's internal configuration register sets are organized in the particular manner to create that impression to the standard configuration software.) PAC supports PCI configuration space access using the mechanism denoted as configuration mechanism 1 in the PCI specification. .... 3.1.3.3. Mapping of Configuration Cycles on A.G.P. From the AGPset configuration perspective, A.G.P. is another PCI bus interface residing on a Secondary Bus side of the "virtual" PCI-to-PCI Bridge embedded within PAC. On the Primary Bus side the "virtual" PCI-to-PCI bridge is attached to the BUS #0. Therefore the Secondary side would be denoted as a BUS#1 in the system where configuration software would scan devices on the PCI bus #0 going from the lowest (0) to the highest (20) device number. The "virtual" PCI-to-PCI bridge entity is used to map Type #1 PCI Bus Configuration cycles directed to BUS #0 onto the Type #0 or Type #1 configuration cycles on the A.G.P. interface ...." ------- end of quota ----------