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To: Pravin Kamdar who wrote (6302)	5/23/1998 3:04:00 PM
From: Pravin Kamdar	Read Replies (2) \| Respond to of 6843

From this roadmap, amd.com it looks like the K6-3 (Sharptooth) will not only integrate an L2 cache, but also utilize a frontside L3 cache. Doesn't the Alpha bus use this type of bus technology? Any comments on potential performance? This could be a killer chip in 2H '98. Pravin.

To: Pravin Kamdar who wrote (6302)	5/23/1998 4:11:00 PM
From: Yousef	Read Replies (1) \| Respond to of 6843

Pravin, Re: "Also, why would you expect the voltages to be any different than with the K6?" The reason I expected different voltages is because original info from AMD indicated that the K6-3D would be offered at 350mhz. I believe this will require AMD to either "jack up" the supply voltage with their current FET or AMD will re-design their .35um FET so that a lower voltage is used. I posted my concerns to Paul earlier this month: Message 4494532 "I also find it interesting that AMD has not been HYPE'ing the K6-ME-2 ... I wonder if the 350mhz speed bin is proving to be difficult for them. Wouldn't be interesting if AMD was only able to come out with 300mhz and maybe 333mhz CPU's. We will all know soon." Make It So, Yousef