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To: Dave Hanson who wrote (827)5/25/1998 2:20:00 PM
From: LTBH  Read Replies (1) | Respond to of 14778
 
333 Circuits

Except from c't Magazine article, could not find the discussion I was looking for, that indicates a bit slower real world app throughput and other circuit changes made.

ix.de

Restricted L2 cache

The most obvious changes were made in the 512 KByte L2 cache that resides on the processor module. It still runs at half the processor clock, but now only consists of three components: the Tag-RAM (Intel S82459AC) and two regular Burst-Cache chips. On our evaluation model these came from Samsung (SEC KM736V604). The old Pentium uses five chips: one Tag component (S82459AB) and four cache ICs (SEC KM732V595 or KM736V595).

Reducing components lowers the costs and power consumption, but it also inhibits the performance: four chips - organized in 32K x 32 - allow building two 64-bit wide cache blocks, that the CPU can access in turns in an interleaved mode. During consecutive accesses this saves a few clocks and thus is faster.

Therefore at 300 MHz the L2 cache of Deschutes runs about four percent slower than a regular Pentium II. Accordingly at 333 MHz the advantage of the L2 throughput compared to a PII-300 is not ten percent but only seven percent.

Networm