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To: Investor A who wrote (6358)	5/28/1998 3:37:00 PM
From: DragonBoy	Read Replies (2) \| Respond to of 6843

InvesterA, Let me add "here" to 3DNOW ====> it becomes 3DNoWhere. Hehehehe.(TM DragonBoy).

To: Investor A who wrote (6358)	5/28/1998 11:24:00 PM
From: Time Traveler	Read Replies (1) \| Respond to of 6843

Fuchi, you absolutely have your head in the clouds. >>"The users of PII SLOT 1 board will be limited to the tinny 512K."<< Intel already have P-II with 1M or 2M L2 cache aimed for the server market. >>64K L1 and 256K L2 Running at Core Speed, 1M (2M) L3 Cache Running at 100~133MHz<< This would be a total waster of money for the 1M and 2M L3 cache. Notice the ratio of L1 to L2 is 1:4, not very practical., and the L3 cache is not using a dedicated bus. The advantage of Slot-I over Socket-7 is very obvious regardless whether AMD can deliver K6-n as promised (n being a natural number greater or equal to 3). Time Traveler says "Socket-7 is not good enough".