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To: kemble s. matter who wrote (45354)	5/29/1998 3:15:00 PM
From: Bandit19	Read Replies (3) \| Respond to of 176387

Kemble, Hi!....DELL @83 1/8 holding steady, like a steel beam.... Do you love this stock or what???... Staying the course cause Mikey doesn't lie!!!...Steve

To: kemble s. matter who wrote (45354)	5/29/1998 3:43:00 PM
From: Meathead	Read Replies (1) \| Respond to of 176387

Upcoming Processors from Intel Courtesy of Kenneth Ekman Katmai Q1 1999 Pentium II including Katmai New Instructions (formerly known as MMX2), with 70 added instructions adding enhanced floating point and 3D capabilities using SIMD FP instructions, larger L1 cache and 512 kB L2 cache, starting at 450 MHz using the 100 MHz bus. The first versions uses the .25 um process and is priced around $700, while later versions will be shrunk to .18 um process and increase the clock speed to around 750 MHz by the year 2000. Analysts have said that Intel is likely to move to a 200 MHz front side bussoon after the introduction to take advantage of the increased bandwidth of Rambus DRAM. Prototype Katmai chips will ship to developers in the summer of 98. Comes in both Slot 1 and Slot 2 versions. Katmai systems are expected to initially cost above $2000. Tanner Q2 1999 IA-32 processor starting at 500 MHz with the Slot-M form factor, to ease the transition to Merced. (Note that some recent sources have put it the other way around, describing the Tanner as a Merced derived core in a slot 2 module.) Sources say that Tanner will also be available in a slot 2 module, perhaps in the Lion32 platform. Intel expects Tanner servers to cost about $6000 and up. Willamette Q4 1999 P6 enhanced for speed in a number of ways, for example added decoders, execution units, larger buffers and larger cache. Will according to Intel sources be around 30 - 50 % faster than Deschutes at the same core speed. Starts at 0.18 um shrinking to 0.13 after the turn of the century while clock speed increases from 600 MHz to 1.2 GHz. Can be seen as a new generation (P6.5?). May be the last IA-32 processor. May also include new bus concepts earlier only found in Dec Alpha etc. Q4 Merced... Q4 of 1999 The first processor coming out of the HP / Intel cooperation. Introduces the IA-64 architecture, using the EPIC (Explicitly Parallel Instruction Computing) technology. IA-64 leaves the optimization work to the compiler but the compiled code includes information about inherent parallelism. This has the drawback of making compiled code more processor specific (optimisation-wise), but reduces the need to fill the chip with logic to analyse and reorganize the code during runtime. It remains to be seen how Intel has been able to balance the architecture. It will also be IA-32 compatible in hardware, although later IA-64 products may use software translation. Includes 4 floating point units while the die size may run up to 300 mm2 using a 0.18 um process. Rumored to start at around 800 MHz clock speed with the 128 bit Slot-M bus most likely running at 200 MHz, providing a peak bandwidth of 3.2 Gb/s. Priced between $1500 to $2000. This is supposed to get Intel processors into the next decade. McKinley / Flagstaff 2001 The second generation IA-64 chip, McKinley will likely start around 1GHz. HP is said to be more active in the development of this chip than it has been in Merced. Will roughly double Merced's performance. Some rumors even speculate that HP and DEC may discontinue their own 64 bit architectures in favor of IA-64 at this time. MEATHEAD