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To: Mason Barge who wrote (1034)	5/30/1998 10:54:00 AM
From: TI2, TechInvestorToo	Respond to of 1305

Mason, Robert Grutza has asserted that Merced is not to silicon yet. Check him on cymi thread. I do not know what ground rules are used for Merced (start at 220nm and go to 180?) Also I believe that Micrascan II is the tool in use for 250 nm design rules at INTC. TI2

To: Mason Barge who wrote (1034)	5/30/1998 2:16:00 PM
From: Ian@SI	Respond to of 1305

Does anyone know if Intel is using Micrascan II's on the Merced lines? The current rumor is that the exposure process is causing major problems, specfically due to the light source. If true, bad news for SVGI (and for other equipment suppliers, as it will mean pushouts), but good news for Cymer and maybe another stepper/scanner co. Mason, If the "light source" is causing Intel "major problems" with Merced, then the solution would be to go to the local hardware store and get some new fluorescent bulbs. Today's Interactive WSJ (Front Section) gives a clear description of where INTC is in the MERCED development process. Specifically, they've satisfied with the architectural concept for the processor and are nearing completion of the first design of the physical chip layout. In other words, no MERCED chip is anywhere close to being patterned onto a wafer. Intel merely has a much better idea of how much more effort is required before they'll produce working 64 bit processors. The only part that isn't business as usual is that Intel publicly announced the Merced targets about 1 1/2 years ago rather than waiting until they had a 'bird in the hand'. Anybody who states that a particular piece of equipment or process is causing the delay is either very psychic or "full or it". FWIW, Ian.