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To: Stoctrash who wrote (33587)	6/3/1998 5:30:00 PM
From: John Rieman	Respond to of 50808

MPEG chips that use less memory.............................. eet.com Posted: 3:00 p.m., EST, 6/3/98 MPEG decoders to take less memory with new scheme By Junko Yoshida LOS ANGELES - Digital TV has turned the corner and has changed from a promising consumer technology to a practical design challenge for both system and IC design engineers. A novel memory-reduction algorithm is being developed for integration into future MPEG-2 decoder ICs. Leading MPEG-2 decoder vendors, including Philips Semiconductors, STMicroelectronics, Mitsubishi Electric Corp. and Toshiba Corp., each described their own unique memory-compression schemes at the DTV decoder paper session on Tuesday. to big crowds attending the 1998 International Conference on Consumer Electronics (ICCE) here this week . Because the feature could be applied to MPEG-2 chips for either Main Profile @ Main Level decoding based on standard-definition digital TV (SDTV) or Main Profile @ High Level for high-definition digital TV (HDTV), it could become a crucial solution for today's system designers, as consumer electronics manufacturers wrestle with the development of costly digital HDTV systems while the DVD and set-top markets grow ever more price competitive. Despite the diverging paths and algorithms pursued by various decoder IC vendors, their ultimate goal for the memory-reduction scheme is the same: to reduce the amount of memory required for MPEG decoding and leave enough memory and memory bandwidth for DTV graphics and other user interface applications. Ultimately, the scheme could lead to a unified memory architecture for DTV. That's no trivial task, however, since it would need to be accomplished with a minimal loss of image quality without greatly increasing the overall complexity of an MPEG decoder IC that integrates the memory-reduction scheme. Mitsubishi's new memory-compression algorithm will be key to the company's second-generation, single-chip HDTV decoder due for launch in the second quarter of next year, said Tommy Poon, senior vice president of strategic planning at Mitsubishi Electric America (Sunnyvale, Calif.). The company's first-generation two-piece digital HDTV decoder chip set, which Mitsubishi developed with Lucent Technologies, does not include the memory-reduction scheme. In the conventional method of obtaining a low-resolution image sequence, the high-definition bitstream is fully decoded, then pre-filtered and sub-sampled. This approach maintains high-quality pictures since the full-resolution blocks are stored into memory, but the cost of maintaining a large amount of memory to meet this requirement is an obvious drawback. Mitsubishi has designed a new decoder architecture under which three-layers of resolution - full-memory; half-memory; and quarter-memory - can be decoded using less memory for lower-resolution layers. Mitsubishi has further developed optimal motion-compensation filtering to reduce artifacts - typically known as prediction drift. Although the filtering doesn't totally eliminate the artifacts, a much higher-quality output can be achieved than with simple interpolation methods, said Anthony Vetro, on staff at Mitsubishi's Advanced Television Laboratory (New Providence, N.J.). reducing memory for video decoding, Poon said, "we want to make room for other user-friendly advanced graphics features" that are likely to be in a higher demand for second-generation DTV sets. In addition, a plan to marry an MPEG-2 decoder IC with embedded DRAM is quietly brewing among companies such as Philips and Mitsubishi. "We are looking right now if it's possible to apply the embedded DRAM technology for our second generation DTV decoder chip," Mitsubishi's Poon said.