June 08, 1998, TechWeb News
--------------------------------------------------------------------------------
Ideal for portables; density gains sought -- Designers eye new chip-scale methods
By Terry Costlow
Chip-scale packaging is still in its infancy, but the technology is moving forward quickly. Memory-chip makers are beginning to adopt the technology and move it into production, sparking a number of advances for future-generation products.
Memory makers are adopting chip-scale packages (CSPs) because they sharply reduce the amount of space needed for today's memory-hungry products. With a size that's no more than 1.2 times the size of the device, CSPs are perfect for portable products and others that have severe space constraints. Hitachi, Intel, Mitsubishi, Rambus and others are racing to get the packages into production.
Now that CSP is gaining acceptance, package designers are coming up with new techniques that increase density even more. Two Hitachi units, the parent operation and Hitachi ULSI Systems, unveiled a novel stacking technique that increases density fourfold.
Hitachi is using what it calls a slanted package mounting to provide that density increase over the thin small-outline packages that were used for flash-memory devices. Flash chips in CSP are attached at a slight angle, so they look somewhat like a fanned-out deck of cards.
"With the slant package, we can quadruple our density," said Anthony Carbone, product marketing manager for nonvolatile memories at Hitachi Semiconductor America (Brisbane, Calif.). "Initially we used TSOPs, then in the second generation we went to tape-carrier packages where we stacked one on top of the other to double the density."
While it might seem that stacking chips on top of each other would provide more density, Carbone explained that that isn't true. "The reason it works is that there is actually more than one memory under the first one," he said. "The second chip is about 80 percent under the first, and the third is about 30 percent under the first chip. One end is elevated 1.5 mm, and that end is held with a bracket that keeps the chips stable so they don't pivot on the solder joint. That was one of the big difficulties. If you move the chip you can break the solder joint."
Hitachi is already moving the technique into production, using it in a PCMCIA card that holds 300 Mbytes. The card's high price tag means it won't see much usage beyond professional photographers with digital cameras and a few others. However, declining prices for flash will eventually mean higher volumes for the card and its packaging technology.
"The price of flash has come down significantly," Carbone said. "It was about $10 per Mbyte a year ago. It's $4-$5 now, and it should fall to about $1 per Mbyte by the year 2000. Right now our cards are $1,200 to $1,500, but in a year and a half, they will be $300-$400."
Other companies are pushing CSP technology in different directions. Many note that since there's not much on the chip other than a tiny substrate-like material, packaging technologies can be attached to wafers. Work here is in its early stages.
"The biggest thing on the horizon is wafer-level technology, which will streamline operations and low cost," said Nader Gamini, package-development manager at Rambus Inc. (Mountain View, Calif.). "In the future, I don't think individually packaged CSPs will be able to compete with wafer-level packages. Today we're seeing prototypes. I think by the year 2000 they will start going into high volumes."
Wafer-scale push
Tessera (San Jose, Calif.), whose packaging technology is used by many memory providers, is pushing to develop wafer-scale packaging for its licensees. The initial versions will be designed simply to speed up the packaging process by packaging all chips on a wafer at once.
"We're working a lot with wafer-level packaging, putting our compliant layer on at wafer level," said Joel Fjelstad, a fellow at Tessera. "This can be extremely powerful. Now that you have a thick copper trace [on the packaging material] that you can use to test a fully assembled chip on the wafer, you can put power and ground on the package, not on the chip. You have to design the chip for this, but it can gain you a lot."
While the technologies are advancing quickly, there are still "some issues with chip scale," Gamini said. "Packaging foundry capacity is somewhat limited today, though it's growing fast. Also, costs are high today. A TSOP costs about 1 cent per lead; a comparable CSP is twice as much today. As volumes grow, we believe they can achieve parity. That may happen in late 1999 or early 2000."
Hitachi's Carbone cited techniques for solving the volume problems that can arise with CSPs using new technologies. Hitachi taps existing strengths to ramp production quickly.
"We've done chip scale in a microBGA package for SRAM, but this is a new twist with tape-carrier packages," Carbone said. "The advantage TCP has over microBGA is the cost of production. We have a lot of volume with TCP."
|
