Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : CYRIX / NSM -- Ignore unavailable to you. Want to Upgrade?

To: Scumbria who wrote (27178)	6/8/1998 12:26:00 AM
From: Paul Engel	Respond to of 33344

Scumbria - Re: "MediaGX is kicking their rear at the low end. " Now that one knocked me right out of my chair! I now know why Cyrix/NSM is racking up those huge profits! Paul

To: Scumbria who wrote (27178)	6/8/1998 12:38:00 AM
From: Joe NYC	Read Replies (2) \| Respond to of 33344

Steve, In a multiprocessor system an onboard memory controller does not make sense. Instead you want to have very large L2 caches to minimize traffic on the system bus. In a multiprocessor system, it would be nice to have 2+ CPUs share one memory controller and one very large L2 cache. With 2+ CPUs, each one it it's own packaging, each CPU needs to check all of the L2s (if I understand it correctly) before it accesses the DRAM. So more CPU's with their own L2's will generate a lot of trafic on the system bus. If anybody understand's this better, please feel free to jump in. Joe