To: MulhollandDrive who wrote (4663 ) 6/18/1998 2:32:00 PM From: REH Read Replies (1) | Respond to of 93625
let's post the entire article - this is good news: SAN FRANCISCO - Intel Corp. said it has tested the initial 64- and 72-Mbit Direct Rambus DRAMs from Toshiba Corp. (Tokyo) and found that they meet Intel's speed targets. Intel confirmed on Tuesday that the parts had passed pipelined read/write testing at the 800-MHz speed, including initialization procedures and power management. Testing of initial silicon from LG Semicon (Seoul, South Korea) is currently in progress at Intel. Intel has not only stuck by the Rambus approach, but has even dropped the idea of using double-data-rate (DDR) DRAMs in graphics subsystems, said a DRAM technology manager for Fujitsu Ltd. The manager said that Fujitsu is also ready with engineering samples of its Direct RDRAMs. Concerns about the die size persist, but Intel confirmed that it saw 1.6-Gbyte/second performance from the initial Toshiba 64- and 72-Mbit DRAMs. Toshiba became the first company to ship engineering samples of the parts in that density this past April, followed by LG Semicon. Peter MacWilliams, director of platform architecture at Intel, issued a statement saying that several more of the 15 licensed DRAM vendors would be providing silicon in the next few weeks. "We believe the industry is still on track to ship Direct RDRAM memory technology in PC platforms in 1999," he said. Intel also tested the module, or RIMM, the pc-board layout, and the chip-scale package used for the RDRAMs, said Subodh Toprani, vice president at Rambus. "The thing we are very gratified about is that the initial silicon from our vendors is working the way we expected it to work," said Toprani. Dell, Compaq ready PCs As part of the announcement, technology officers at both Compaq Computer and Dell Computer issued statements saying that their companies were on track to provide desktops using the Direct Rambus architecture for main memory. Jay Bell, senior fellow at Dell (Austin, Texas), said, "the Direct Rambus program represents the primary technological thrust for system memory in 1999." Toprani said the first Direct RDRAMs were "maximized to hit our performance targets. The first slice were these low-risk parts; the next step is to cut down the die size." By measuring the margin performance in the interface, the row and column drivers and sense amps, companies will be able to optimize their designs and reduce the die-size penalty, compared with the synchronous DRAMs shipping today, he said. Partly because Toshiba and LG Semicon both decided to use a 16-bank architecture for the 64/72-Mbit parts, and because the interface logic has not been optimized, the die-size penalty is negligible. That, and worries that the chip-scale packaging and testing costs will be higher, have led to questions about how fast the RDRAMs will be price-competitive, considering the license fees and royalties involved. Toprani declined to provide details, but said the Rambus goal is to see DRAM vendors reduce the die-size penalty to 5 percent, which he called "a tough target." Toprani also sought to dispel concerns that the cost of testing the RDRAMs would add up significantly. By using a direct-access test mode on the Direct RDRAMs, companies will be able to test the memory-core portion of the chip by using today's garden-variety memory testers. Since the analog-like cores take as long as 10 minutes to test per chip, multiple units of memory testers can be used for that portion. Once the core is tested, the chip can be switched to a higher-cost logic tester, such as the Hewlett-Packard 8300, for the logic interface test, which takes only 10 to 15 seconds. Once the dual-mode memory-logic testers come down in cost, the DRAM vendors probably will move to a single-tester approach.