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To: Jeff Fox who wrote (58456)6/22/1998 2:19:00 PM
From: Paul Engel  Respond to of 186894
 
Jeff & Intel Investors - Intel Has Company - Sun is Delaying their UltraSparc III

For those out there that think Intel's 6 month delay of Merced was the only microprocessor project to slip, the "Big Kahuna" Sun just announced their SLIPPAGE on UltraSparc III.

If anyone is interested, I may be able to find a few choice quotes by Scott McNealy about Intel when Intel announced their Merced delay. I wonder how "cocky" Mr. McNealy is feeling today!

For those who like VERBAL TAP DANCING, please read the following article carefully - especially Sun's "excuses".

Paul

{=========================}

sumnet.com

From Page One of Electronic News: June 22, 1998 Issue

Sun Delays UltraSparc III

Like Intel, firm says it has to do some fine-tuning of its chip

By Jim DeTar

Palo Alto, Calif.--Sun Microsystems has delayed the introduction of its next-generation 64-bit UltraSparc III architecture by at least two to three months, Electronic News has learned. The delay follows on the heels of a similar announcement by Intel, which recently said it will not ship the planned 64-bit Merced microprocessor in volume until the year 2000, a delay of six to nine months from the previous Intel schedule for Merced (EN, June 1).

In a joint interview with EN at Sun headquarters here at the recent third annual Inside Sun Software day, Anant Agrawal, Sun Microelectronics VP of engineering; and Jeff O'Neal, Sun
Microelectronics Sparc group marketing manager, outlined Sun's plans to stave off the Intel challenge in the workstation market. During the interview, Mr. Agrawal revealed that Sun will delay introduction of the UltraSparc III by several months. Although he attributed the delay to routine shakeouts associated with a new architecture, it raises questions as to whether there might be some difficulty getting the new architecture up on the EPIC-5 manufacturing process used by Sun's partner, Texas Instruments. TI will manufacture the first UltraSparc IIIs at the 0.25-micron geometry level.

Sun's Opportunity

Intel has said it will initially target the workstation/server segments with Merced, and later migrate the chip downward into the desktop PC market at the end of life of Pentium.
According to Mr. Agrawal, despite the delay in the introduction of UltraSparc III, Intel's longer delay provides an opportunity for Sun to fine tune the architecture of the next-generation UltraSparc III.

"The UltraSparc II is currently at 360MHz and the UltraSparc III's new architecture, which was introduced at last fall's Microprocessor Forum, will initially be offered at 600MHz at the end of this year. We have moved our introduction date for the UltraSparc III out by two to three months."

At last year's Microprocessor Forum, Sun said it would sample the UltraSparc III by mid-summer '98. Now the company is saying it will have silicon by the end of this year. The delay may disappoint some workstation customers who have been waiting for UltraSparc III,
which is expected at introduction to provide a 2- to 3x performance increase in terms of both integer and floating point performance over UltraSparc II due to its wide memory bandwidth of 2.4 gigabytes/sec.

When asked why Sun had pushed out the introduction date for UltraSparc III, Mr. Agrawal responded, "We wanted to strengthen our design methodology." He said the company has not run into any unusual challenges but rather wanted to fine tune the architecture before
release. "We are still planning on getting the design to silicon before the end of the year," he added.

Mr. O'Neal said that Sun will continue to migrate the performance of UltraSparc II upward as it ramps UltraSparc III. "UltraSparc II will continue to push the microprocessor performance limits and we will go upwards of 500MHz with it. UltraSparc III will initially come out on
0.25-micron manufacturing process and the UltraSparc IV will come out on 0.18-micron."

Sun provided a first look at the UltraSparc III architecture last fall at the 10th annual Microprocessor Forum in San Jose (EN, Oct. 13, 1997). Among the goals for the forthcoming architecture: scalability to 1,000-plus processor systems. Specifications for the soon to be released device include a six-layer metal, 0.25-micron design process, die size of 330 millimeters-squared, power draw of 70 watts at 1.8 volts, transistor count of 16 million consisting of 12 million transistors of RAM memory and 4 million logic transistors, in a
1,200-pin LGA package.

Goals Expected

This architecture is expected to enable UltraSparc III to reach an estimated SPECint95 integer rating of 35 and to push the SPECfp floating point performance rating to 60. The strong floating point measure for the chip will make it suitable for large data-set omputing, such as computer-aided design and manufacturing (CAD/CAM), electronic design automation (EDA) and scientific modeling applications.

Mr. Agrawal said he thinks the upcoming transition to the combined x86/PA-RISC architecture will pose a difficult challenge for Intel in terms of software. "The 860 was the last software transition for Intel. With the combination of PA-RISC and IA-32 with new (64-bit)
instructions, they have a hard problem in terms of verification. There is no legacy software.

"We are simply adding to our verification suite with the UltraSparc III, building on 14 years of experience. UltraSparc III will be our third generation of the Sparc architecture. We are continually doing verification, we have a building here where there are 1,500 to 2,000
machines constantly doing functional verification."

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