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Politics : Formerly About Applied Materials -- Ignore unavailable to you. Want to Upgrade?

To: Clarksterh who wrote (20755)	6/24/1998 5:59:00 PM
From: Teri Skogerboe	Read Replies (1) \| Respond to of 70976

Ok Clark (as you say) -g-, Right off the bat, I have a question about No. 4 on your list, "This year Intel is 100% .25u." I read something very different from this in EET or EBN. What is the source that says Intel is at 100% .25? I even recall from an Intel CC that they weren't fully changed over, but that was 1-2 quarters ago. I vividly remember getting at least one engineer's view on these shrinks, and can probably find that. But, what I'm most interested in is knowing "the real story". Edited. And how many transistors does the Celery chip have?? Goodness, it's no wonder we have trouble getting the scoop on this.

To: Clarksterh who wrote (20755)	6/24/1998 6:34:00 PM
From: Proud_Infidel	Respond to of 70976

Re: INTC shrink designs Paul Engel of the INTC thread is an invaluable source for these types of questions. I will post Teri's question to him. Last time I asked him a specific question, he knew in mm, the size of each INTC design. BK

To: Clarksterh who wrote (20755)	6/24/1998 6:53:00 PM
From: FJB	Read Replies (2) \| Respond to of 70976

Clark, FWIW, the P55C was 128mm&#178 on Intel's 0.35 process and the PII measures in at 131mm&#178 on their 0.25 process. These are the actual die sizes. Celeron and PII have the same core, so no difference in size there. Intel will be the sole manufacturer of the full-speed SRAM that will be packaged with its Xeon processors(from 512K to 2MB). Later in the year, they are adding 128K of L2 cache to the PII die creating Mendocino, which will be a low-priced high-volume part. I'm not sure what the die size penalty will be for adding the 128K cache. Bob