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Politics : Formerly About Applied Materials -- Ignore unavailable to you. Want to Upgrade?

To: Proud_Infidel who wrote (20771)	6/24/1998 11:05:00 PM
From: eabDad	Respond to of 70976

Thanks Brian for posting this informative note. The "shrink" issue is complicated by a few other factors. There is a "photo shrink" and a "layout enhanced shrink". The photo shrink basically uses a smaller linewidth with the same mask set to produce a smaller chip. However, decreased linewidths allow pitch specifications to change which means a more efficient layout can be designed with a different mask set. Take Paul's data: 0.35 to 0.25 micron is 28% 203 to 131 mm2 die size is about a 35% decrease Comparison between the Pentium MMX (socket 7) and the P-II (slot 1) is complicated by the design choice to design the cache SRAM off the chip, onto a PC board, inside the P-II package called slot 1. Meanwhile the P-II has designed in other features more advantageous on-chip to "increase complexity". In the end, Intel is trying to keep the gross die per wafer above 130-150 at introduction in order to keep the production economic on 200mm wafers, not being forced to 300mm wafers. The die size near 200mm2 does this. Since Intel has decided not to migrate to 300mm until at least 0.13 micron, we can assume that Merced will be a 200mm product when introduced coincident with 0.18 micron. Z